文件名称:or1200_uart

  • 所属分类:
  • 串口编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 7.72mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 陶*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

OR1200最小系统,包括软核处理器OR1200,内存,总线,GPIO及UART的RTL实现。在SOPC2000硬件平台上实现。软件开发环境为Ubuntu,能实现SOPC2000和PC机的简单串口通信。-OR1200 minimum system, including soft-core processor OR1200, memory, bus, GPIO and UART of the RTL implementation. In SOPC2000 hardware platform. Software development environment for Ubuntu, PC, to achieve SOPC2000 and simple serial communication.
相关搜索: or1200

(系统自动生成,下载前可以参看下载内容)

下载文件列表

or1200_wb_ram_gpio_pll_uart\gpio\tags\asyst_2\rtl\verilog\gpio_defines.v

...........................\....\....\.......\...\.......\gpio_top.v

...........................\....\....\......3\rtl\verilog\gpio_defines.v

...........................\....\....\.......\...\.......\gpio_top.v

...........................\....\....\rel_1\bench\verilog\clkrst.v

...........................\....\....\.....\.....\.......\gpio_mon.v

...........................\....\....\.....\.....\.......\tb_defines.v

...........................\....\....\.....\.....\.......\tb_tasks.v

...........................\....\....\.....\.....\.......\tb_top.v

...........................\....\....\.....\.....\.......\timescale.v

...........................\....\....\.....\.....\.......\wb_master.v

...........................\....\....\.....\doc\gpio_spec.pdf

...........................\....\....\.....\...\src\gpio_spec.doc

...........................\....\....\.....\rtl\verilog\gpio_defines.v

...........................\....\....\.....\...\.......\gpio_top.v

...........................\....\....\.....\sim\rtl_sim\bin\sim.sh

...........................\....\....\.....\.yn\bin\cons_art_umc18.inc

...........................\....\....\.....\...\...\cons_vs_umc18.inc

...........................\....\....\.....\...\...\read_design.inc

...........................\....\....\.....\...\...\reports.inc

...........................\....\....\.....\...\...\save_design.inc

...........................\....\....\.....\...\...\select_tech.inc

...........................\....\....\.....\...\...\set_env.inc

...........................\....\....\.....\...\...\tech_art_umc18.inc

...........................\....\....\.....\...\...\tech_vs_umc18.inc

...........................\....\....\.....\...\...\top_gpio.scr

...........................\....\....\.....\...\run\dodesign

...........................\....\....\.....0\bench\verilog\clkrst.v

...........................\....\....\......\.....\.......\gpio_mon.v

...........................\....\....\......\.....\.......\gpio_testbench.v

...........................\....\....\......\.....\.......\tb_defines.v

...........................\....\....\......\.....\.......\tb_tasks.v

...........................\....\....\......\.....\.......\timescale.v

...........................\....\....\......\.....\.......\wb_master.v

...........................\....\....\......\doc\gpio_spec.pdf

...........................\....\....\......\...\src\gpio_spec.doc

...........................\....\....\......\rtl\verilog\gpio_defines.v

...........................\....\....\......\...\.......\gpio_top.v

...........................\....\....\......\sim\rtl_sim\bin\cds.lib

...........................\....\....\......\...\.......\...\hdl.var

...........................\....\....\......\...\.......\...\INCA_libs\worklib\inca.linux.138.pak

...........................\....\....\......\...\.......\...\rtl_file_list

...........................\....\....\......\...\.......\...\sim.sh

...........................\....\....\......\...\.......\...\sim_file_list

...........................\....\....\......\...\.......\log\ncelab.log

...........................\....\....\......\...\.......\...\ncsim.log

...........................\....\....\......\...\.......\...\ncvlog.log

...........................\....\....\......\...\.......\run\ncelab.args

...........................\....\....\......\...\.......\...\ncsim.args

...........................\....\....\......\...\.......\...\ncsim.tcl

...........................\....\....\......\...\.......\...\ncvlog.args

...........................\....\....\......\...\.......\...\run_sim

...........................\....\....\......\.yn\bin\cons_art_umc18.inc

...........................\....\....\......\...\...\cons_vs_umc18.inc

...........................\....\....\......\...\...\read_design.inc

...........................\....\....\......\...\...\reports.inc

...........................\....\....\......\...\...\save_design.inc

...........................\....\....\......\...\...\select_tech.inc

...........................\....\....\......\.

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