文件名称:RD1008

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 716kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • muruga*******
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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Receiver module design i am uploding it thax
(系统自动生成,下载前可以参看下载内容)

下载文件列表

RD1008\Docs\rd1008.pdf

......\....\RD1008_readme.txt

......\Project\MACH4A3\verilog\pci_target_33mhz_verilog_mach4a3.lci

......\.......\.......\.......\pci_target_33mhz_verilog_mach4a3.lct

......\.......\.......\.......\pci_target_33mhz_verilog_mach4a3.sty

......\.......\.......\.......\pci_target_33mhz_verilog_mach4a3.syn

......\.......\.......\.......\pci_tb_tfa.udo

......\.......\.......\.......\pci_tb_tffa.udo

......\.......\.......\.hdl\pci_target_33mhz_vhdl_mach4a3.lci

......\.......\.......\....\pci_target_33mhz_vhdl_mach4a3.lct

......\.......\.......\....\pci_target_33mhz_vhdl_mach4a3.sty

......\.......\.......\....\pci_target_33mhz_vhdl_mach4a3.syn

......\.......\.......\....\pci_tb_vhda.udo

......\.......\.......\....\pci_tb_vhdaf.udo

......\.......\xo\verilog\pci_target_33mhz_verilog.lpf

......\.......\..\.......\pci_target_33MHz_verilog.syn

......\.......\..\.......\pci_tb_tf.udo

......\.......\..\.......\pci_tb_tff.udo

......\.......\..\.......\pci_tb_tfr.udo

......\.......\..\.hdl\pci_target_33mhz_vhdl.lpf

......\.......\..\....\pci_target_33mhz_vhdl.syn

......\.......\..\....\pci_tb_vhd.udo

......\.......\..\....\pci_tb_vhdf.udo

......\.......\..\....\pci_tb_vhdr.udo

......\.......\.p2\verilog\pci_target_33mhz_verilog.lpf

......\.......\...\.......\pci_target_33mhz_verilog.syn

......\.......\...\.......\pci_tb_tf.udo

......\.......\...\.......\pci_tb_tff.udo

......\.......\...\.......\pci_tb_tfr.udo

......\.......\...\.hdl\pci_target_33mhz_vhdl.lpf

......\.......\...\....\pci_target_33mhz_vhdl.syn

......\.......\...\....\pci_tb_vhd.udo

......\.......\...\....\pci_tb_vhdf.udo

......\.......\...\....\pci_tb_vhdr.udo

......\Source\verilog\base_addr_chk.v

......\......\.......\config_mux.v

......\......\.......\glue.v

......\......\.......\pargen.v

......\......\.......\pci_top.v

......\......\.......\retry_count.v

......\......\.......\state_machine.v

......\......\.hdl\base_addr_chk.vhd

......\......\....\config_mux.vhd

......\......\....\glue.vhd

......\......\....\pargen.vhd

......\......\....\pci_top.vhd

......\......\....\retry_count.vhd

......\......\....\state_machine.vhd

......\Testbench\verilog\bkend_daemon.v

......\.........\.......\pci_clk_reset.v

......\.........\.......\pci_stim.v

......\.........\.......\pci_tb.v

......\.........\.......\tasks.v

......\.........\......._for_classic\pci_tb.v

......\.........\.hdl\bkend_daemon.vhd

......\.........\....\lattice_lib.vhd

......\.........\....\pci_clk_reset.vhd

......\.........\....\pci_stim.vhd

......\.........\....\pci_tb.vhd

......\.........\...._for_classic\pci_tb.vhd

......\Project\MACH4A3\verilog

......\.......\.......\vhdl

......\.......\xo\verilog

......\.......\..\vhdl

......\.......\.p2\verilog

......\.......\...\vhdl

......\.......\MACH4A3

......\.......\xo

......\.......\xp2

......\Source\verilog

......\......\vhdl

......\Testbench\verilog

......\.........\verilog_for_classic

......\.........\vhdl

......\.........\vhdl_for_classic

......\Docs

......\Project

......\Source

......\Testbench

RD1008

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