文件名称:FPGA-PWM

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 253kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 于*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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用FPGA实现PWM信号生成,目前还是比较热门。也是很好的参考资料-PWM signal generation with the FPGA implementation, is still more popular. Is also a good reference
相关搜索: fpga
pwm
FPGA
PWM
PWM
PWM
FPGA
PWM
FPGA

(系统自动生成,下载前可以参看下载内容)

下载文件列表

an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code\pwm_main.v

....................\.............................................................\modelsim\pulse_width_modulator.cr.mti

....................\.............................................................\........\pulse_width_modulator.mpf

....................\.............................................................\........\pwm_main.v

....................\.............................................................\........\pwm_sim.cr.mti

....................\.............................................................\........\pwm_sim.mpf

....................\.............................................................\........\test_pwm.v

....................\.............................................................\........\wave.bmp

....................\.............................................................\........\wave.do

....................\.............................................................\........\wave2.bmp

....................\.............................................................\........\wave2.do

....................\.............................................................\........\wave3.bmp

....................\.............................................................\........\wave3.do

....................\.............................................................\........\wave4.bmp

....................\.............................................................\........\wave4.do

....................\.............................................................\........\wave5.bmp

....................\.............................................................\........\wave5.do

....................\.............................................................\........\.ork\altufm_osc0_altufm_osc_1p3\verilog.asm

....................\.............................................................\........\....\..........................\_primary.dat

....................\.............................................................\........\....\..........................\_primary.vhd

....................\.............................................................\........\....\clkgen\verilog.asm

....................\.............................................................\........\....\......\_primary.dat

....................\.............................................................\........\....\......\_primary.vhd

....................\.............................................................\........\....\..._gen\verilog.asm

....................\.............................................................\........\....\.......\_primary.dat

....................\.............................................................\........\....\.......\_primary.vhd

....................\.............................................................\........\....\dutycycle\verilog.asm

....................\.............................................................\........\....\.........\_primary.dat

....................\.............................................................\........\....\.........\_primary.vhd

....................\.............................................................\........\....\...._cycle\verilog.asm

....................\.............................................................\........\....\..........\_primary.dat

....................\.............................................................\........\....\..........\_primary.vhd

....................\.............................................................\........\....\pwm_gen\verilog.asm

....................\.............................................................\........\....\.......\_primary.dat

....................\.............................................................\........\....\.......\_primary.vhd

....................\.............................................................\........\....\....main\verilog.asm

....................\..

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