文件名称:veriloguart

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 382kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • zhan****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

简易的串口模块儿驱动程序,用verilog语言描述,自己可以进行增加或裁剪-verilog uart
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart\device_usage_statistics.html

....\uart.bgn

....\uart.bit

....\uart.bld

....\uart.cmd_log

....\uart.drc

....\uart.ise

....\uart.lso

....\uart.ncd

....\uart.ngc

....\uart.ngd

....\uart.ngr

....\uart.ntrc_log

....\uart.pad

....\uart.par

....\uart.pcf

....\uart.prj

....\uart.ptwx

....\uart.restore

....\uart.stx

....\uart.syr

....\uart.twr

....\uart.twx

....\uart.unroutes

....\uart.ut

....\uart.xpi

....\uart.xst

....\uart1.v

....\uart_control.v

....\uart_guide.ncd

....\uart_map.map

....\uart_map.mrp

....\uart_map.ncd

....\uart_map.ngm

....\uart_map.xrpt

....\uart_ngdbuild.xrpt

....\uart_pad.csv

....\uart_pad.txt

....\uart_par.xrpt

....\uart_prev_built.ngd

....\uart_summary.xml

....\uart_usage.xml

....\.....xdb\cst.xbcd

....\........\tmp\ise\version

....\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject

....\........\...\...\............\..................\.........\HDProject_StrTbl

....\........\...\...\............\..................\__stored_object_table__

....\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl

....\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl

....\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main

....\........\...\...\............\................\................\dpm_project_main_StrTbl

....\........\...\...\............\................\__stored_objects__

....\........\...\...\............\................\__stored_objects___StrTbl

....\........\...\...\............\................\__stored_object_table__

....\........\...\...\............\................Gui\GuiProjectData

....\........\...\...\............\...................\GuiProjectData_StrTbl

....\........\...\...\..REGISTRY__\Autonym\regkeys

....\........\...\...\............\bitgen\regkeys

....\........\...\...\............\common\regkeys

....\........\...\...\............\.pldfit\regkeys

....\........\...\...\............\Cs\regkeys

....\........\...\...\............\dumpngdio\regkeys

....\........\...\...\............\fuse\regkeys

....\........\...\...\............\HierarchicalDesign\HDProject\regkeys

....\........\...\...\............\..................\regkeys

....\........\...\...\............\hprep6\regkeys

....\........\...\...\............\idem\regkeys

....\........\...\...\............\map\regkeys

....\........\...\...\............\netgen\regkeys

....\........\...\...\............\.gc2edif\regkeys

....\........\...\...\............\...build\regkeys

....\........\...\...\............\..dbuild\regkeys

....\........\...\...\............\par\regkeys

....\........\...\...\............\ProjectNavigator\regkeys

....\........\...\...\............\................Gui\regkeys

....\........\...\...\............\runner\regkeys

....\........\...\...\............\SrcCtrl\regkeys

....\........\...\...\............\.TE\bitgen\regkeys

....\........\...\...\............\...\map\regkeys

....\........\...\...\............\...\ngdbuild\regkeys

....\........\...\...\............\...\par\regkeys

....\........\...\...\............\...\regkeys

....\........\...\...\............\...\trce\regkeys

....\........\...\...\............\...\xst\regkeys

....\........\...\...\............\taengine\regkeys

....\........\...\...\............\.rce\regkeys

....\........\...\...\............\.sim\regkeys

....\........\...\...\............\vhpcomp\regkeys

....\........\...\...\............\.logcomp\regkeys

....\........\...\...\............\WebTalk\DesignDataCollection\regkeys

....\........\...\...\............\.......\regkeys

....\........\...\...\............\xpwr\regkeys

....\........\...\...\............\XSLTProcess\regkeys

....\........\...\...\............\xst\regkeys

....\........\...\...\............\_ProjRepoInternal_\regkeys

....\........\...\ise.lock

....\uart_xst.xrpt

....\xst\dump.xst\uart.prj\ntrc.scr

....\...\work\hdllib.ref

....\...\....\vlg48\uart.bin

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