文件名称:LIP4301CORE_PCI

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 164kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • j*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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PCI Verilog source code
相关搜索: verilog
PCI
LIP4301CORE_PCI

(系统自动生成,下载前可以参看下载内容)

下载文件列表

LIP4301CORE_PCI\core_rtl\CVS\Entries

...............\........\...\Repository

...............\........\...\Root

...............\........\pcix_bytectrl.v

...............\........\pcix_conf.v

...............\........\pcix_confchk.v

...............\........\pcix_confctrl.v

...............\........\pcix_dma.v

...............\........\pcix_dmactrl.v

...............\........\pcix_dpram.v

...............\........\pcix_inmux.v

...............\........\pcix_masterctrl.v

...............\........\pcix_mastermux.v

...............\........\pcix_mastersm.v

...............\........\pcix_megabar.v

...............\........\pcix_miscreg.v

...............\........\pcix_modedetect.v

...............\........\pcix_mtcore.v

...............\........\pcix_par36.v

...............\........\pcix_parity.v

...............\........\pcix_phasecount.v

...............\........\pcix_phasectrl.v

...............\........\pcix_powermgt.v

...............\........\pcix_rombar.v

...............\........\pcix_roundrobin.v

...............\........\pcix_screg.v

...............\........\pcix_split.v

...............\........\pcix_targetsm.v

...............\.....tb\CVS\Entries

...............\.......\...\Repository

...............\.......\...\Root

...............\.......\pcixtb_arbiter.v

...............\.......\pcixtb_monitor.v

...............\.......\pcixtb_pcix_script.v

...............\.......\pcixtb_pcix_target.v

...............\.......\pcixtb_pcix_targetsm.v

...............\.......\pcixtb_pci_script.v

...............\.......\pcixtb_pci_target.v

...............\.......\pcixtb_targetbar.v

...............\.......\pcix_testb.v

...............\.......\pkg_pcix_testb.v

...............\.......\transcript

...............\CVS\Entries

...............\...\Repository

...............\...\Root

...............\Logical Intellectual Properity Core_1.pdf

...............\ref_design\async_apff.v

...............\..........\async_paff.v

...............\..........\CVS\Entries

...............\..........\...\Repository

...............\..........\...\Root

...............\..........\dma_mgt.v

...............\..........\dummy_read.v

...............\..........\int_sram_mgt.v

...............\..........\led_mgt.v

...............\..........\pa_rxif.v

...............\..........\pa_txif.v

...............\..........\pcix_core_inst.v

...............\..........\plda_dcfifo.v

...............\..........\plda_dpram.v

...............\..........\R32X32M1.v

...............\..........\ref_design.v

...............\..........\ressources_mgt.v

...............\core_rtl\CVS

...............\.....tb\CVS

...............\ref_design\CVS

...............\core_rtl

...............\core_tb

...............\CVS

...............\ref_design

LIP4301CORE_PCI

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