文件名称:LIP6111CORE_ide_dvd
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下载文件列表
CVS\Entries
...\Repository
...\Root
ide_dvd_1\dma_fifo.v
.........\dma_ide.v
.........\dma_ide_pbif.v
.........\dvd.v
.........\dvd_dma.v
.........\dvd_dma_pbif.v
.........\dvd_fsm.v
.........\dvd_hif.v
.........\dvd_pb.v
.........\dvd_rxdma.v
.........\dvd_rxdma_fifo.v
.........\dvd_rxdma_fifo_summary.html
.........\dvd_sync.v
.........\dvd_top.v
.........\halfduplex.v
.........\ide.v
.........\ide_ctrl.v
.........\ide_dmaif.v
.........\ide_dvd.v
.........\ide_dvd_1.dhp
.........\ide_dvd_1.ise
.........\ide_dvd_1.ise_ISE_Backup
.........\ide_dvd_mux.v
.........\ide_hstcrc.v
.........\ide_intr.v
.........\ide_pbif.v
.........\ide_sm.v
.........\ide_syncdma.v
.........\ide_top.v
.........\ide_tran.v
.........\Project.dhp
.........\__projnav\ide_dvd_1.gfl
.........\.........\sumrpt_tcl.rsp
sub\CVS\Entries
...\...\Repository
...\...\Root
...\dvd_top\CVS\Entries
...\.......\...\Repository
...\.......\...\Root
...\.......\dvd_top.v
...\.......\hdl\CVS\Entries
...\.......\...\...\Repository
...\.......\...\...\Root
...\.......\...\dvd.v
...\.......\...\dvd_dma.v
...\.......\...\dvd_dma_pbif.v
...\.......\...\dvd_fsm.v
...\.......\...\dvd_hif.v
...\.......\...\dvd_pb.v
...\.......\...\dvd_rxdma.v
...\.......\...\dvd_rxdma_fifo.v
...\.......\...\dvd_sync.v
...\.......\syn\artisan_tsmc15lv\.cvsignore
...\.......\...\................\CVS\Entries
...\.......\...\................\...\Repository
...\.......\...\................\...\Root
...\.......\...\................\dvd_top_elaborate.tcl
...\.......\...\................\dvd_top_formal_verif.tcl
...\.......\...\................\dvd_top_setup.tcl
...\.......\...\................\Makefile
...\.......\...\................\synthesis\dvd_top.db
...\.......\...\................\work_lib\clock_tree_hook%verilog.syn
...\.......\...\................\........\clock_tree_hook%verilog__verilog.syn
...\.......\...\................\........\CLOCK_TREE_HOOK.mr
...\.......\...\................\........\dvd%verilog.syn
...\.......\...\................\........\dvd%verilog__verilog.syn
...\.......\...\................\........\DVD.mr
...\.......\...\................\........\dvd_dclk_gen%verilog.syn
...\.......\...\................\........\dvd_dclk_gen%verilog__verilog.syn
...\.......\...\................\........\DVD_DCLK_GEN.mr
...\.......\...\................\........\dvd_dma%verilog.syn
...\.......\...\................\........\dvd_dma%verilog__verilog.syn
...\.......\...\................\........\DVD_DMA.mr
...\.......\...\................\........\dvd_dma_pbif%verilog.syn
...\.......\...\................\........\dvd_dma_pbif%verilog__verilog.syn
...\.......\...\................\........\DVD_DMA_PBIF.mr
...\.......\...\................\........\dvd_fsm%verilog.syn
...\.......\...\................\........\dvd_fsm%verilog__verilog.syn
...\.......\...\................\........\DVD_FSM.mr
...\.......\...\................\........\dvd_hif%verilog.syn
...\.......\...\................\........\dvd_hif%verilog__verilog.syn
...\.......\...\................\........\DVD_HIF.mr
...\.......\...\................\........\dvd_pb%verilog.syn
...\.......\...\................\........\dvd_pb%verilog__verilog.syn
...\.......\...\................\........\DVD_PB.mr
...\.......\...\................\........\dvd_rxdma%verilog.syn
...\.......\...\................\........\dvd_rxdma%verilog__verilog.syn
...\.......\...\................\........\DVD_RXDMA.mr
...\.......\...\................\........\dvd_rxdma_fifo%verilog.syn
...\.......\...\................\........\dvd_rxdma_fifo%verilog__verilog.syn
...\.......\...\................\........\DVD_RXDMA_FIFO.mr
...\.......\...\................\........\dvd_serial%verilog.syn
...\.......\...\................\........\dvd_serial%verilog__verilog.syn
...\.......\...\................\........\DVD_SERIAL.mr
...\.......\...\................\........\dvd_sync%verilog.syn
...\.......\...\................\........\dvd_sync%verilog__verilog.syn
...\.......\...\................\........\DVD_SYNC.mr
...\Repository
...\Root
ide_dvd_1\dma_fifo.v
.........\dma_ide.v
.........\dma_ide_pbif.v
.........\dvd.v
.........\dvd_dma.v
.........\dvd_dma_pbif.v
.........\dvd_fsm.v
.........\dvd_hif.v
.........\dvd_pb.v
.........\dvd_rxdma.v
.........\dvd_rxdma_fifo.v
.........\dvd_rxdma_fifo_summary.html
.........\dvd_sync.v
.........\dvd_top.v
.........\halfduplex.v
.........\ide.v
.........\ide_ctrl.v
.........\ide_dmaif.v
.........\ide_dvd.v
.........\ide_dvd_1.dhp
.........\ide_dvd_1.ise
.........\ide_dvd_1.ise_ISE_Backup
.........\ide_dvd_mux.v
.........\ide_hstcrc.v
.........\ide_intr.v
.........\ide_pbif.v
.........\ide_sm.v
.........\ide_syncdma.v
.........\ide_top.v
.........\ide_tran.v
.........\Project.dhp
.........\__projnav\ide_dvd_1.gfl
.........\.........\sumrpt_tcl.rsp
sub\CVS\Entries
...\...\Repository
...\...\Root
...\dvd_top\CVS\Entries
...\.......\...\Repository
...\.......\...\Root
...\.......\dvd_top.v
...\.......\hdl\CVS\Entries
...\.......\...\...\Repository
...\.......\...\...\Root
...\.......\...\dvd.v
...\.......\...\dvd_dma.v
...\.......\...\dvd_dma_pbif.v
...\.......\...\dvd_fsm.v
...\.......\...\dvd_hif.v
...\.......\...\dvd_pb.v
...\.......\...\dvd_rxdma.v
...\.......\...\dvd_rxdma_fifo.v
...\.......\...\dvd_sync.v
...\.......\syn\artisan_tsmc15lv\.cvsignore
...\.......\...\................\CVS\Entries
...\.......\...\................\...\Repository
...\.......\...\................\...\Root
...\.......\...\................\dvd_top_elaborate.tcl
...\.......\...\................\dvd_top_formal_verif.tcl
...\.......\...\................\dvd_top_setup.tcl
...\.......\...\................\Makefile
...\.......\...\................\synthesis\dvd_top.db
...\.......\...\................\work_lib\clock_tree_hook%verilog.syn
...\.......\...\................\........\clock_tree_hook%verilog__verilog.syn
...\.......\...\................\........\CLOCK_TREE_HOOK.mr
...\.......\...\................\........\dvd%verilog.syn
...\.......\...\................\........\dvd%verilog__verilog.syn
...\.......\...\................\........\DVD.mr
...\.......\...\................\........\dvd_dclk_gen%verilog.syn
...\.......\...\................\........\dvd_dclk_gen%verilog__verilog.syn
...\.......\...\................\........\DVD_DCLK_GEN.mr
...\.......\...\................\........\dvd_dma%verilog.syn
...\.......\...\................\........\dvd_dma%verilog__verilog.syn
...\.......\...\................\........\DVD_DMA.mr
...\.......\...\................\........\dvd_dma_pbif%verilog.syn
...\.......\...\................\........\dvd_dma_pbif%verilog__verilog.syn
...\.......\...\................\........\DVD_DMA_PBIF.mr
...\.......\...\................\........\dvd_fsm%verilog.syn
...\.......\...\................\........\dvd_fsm%verilog__verilog.syn
...\.......\...\................\........\DVD_FSM.mr
...\.......\...\................\........\dvd_hif%verilog.syn
...\.......\...\................\........\dvd_hif%verilog__verilog.syn
...\.......\...\................\........\DVD_HIF.mr
...\.......\...\................\........\dvd_pb%verilog.syn
...\.......\...\................\........\dvd_pb%verilog__verilog.syn
...\.......\...\................\........\DVD_PB.mr
...\.......\...\................\........\dvd_rxdma%verilog.syn
...\.......\...\................\........\dvd_rxdma%verilog__verilog.syn
...\.......\...\................\........\DVD_RXDMA.mr
...\.......\...\................\........\dvd_rxdma_fifo%verilog.syn
...\.......\...\................\........\dvd_rxdma_fifo%verilog__verilog.syn
...\.......\...\................\........\DVD_RXDMA_FIFO.mr
...\.......\...\................\........\dvd_serial%verilog.syn
...\.......\...\................\........\dvd_serial%verilog__verilog.syn
...\.......\...\................\........\DVD_SERIAL.mr
...\.......\...\................\........\dvd_sync%verilog.syn
...\.......\...\................\........\dvd_sync%verilog__verilog.syn
...\.......\...\................\........\DVD_SYNC.mr