文件名称:EDAdianzizhong
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基于FPGA的数字电子钟设计，有VHDL语言实现其功能-FPGA-based design of digital electronic clock with VHDL language function
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下载文件列表
EDA电子钟\123.txt
.........\clock.asm.rpt
.........\clock.done
.........\clock.fit.rpt
.........\clock.fit.smsg
.........\clock.fit.summary
.........\clock.flow.rpt
.........\clock.map.rpt
.........\clock.map.summary
.........\clock.pin
.........\clock.pof
.........\clock.qpf
.........\clock.qsf
.........\clock.qws
.........\clock.sim.rpt
.........\clock.sof
.........\clock.tan.rpt
.........\clock.tan.summary
.........\clock.vhd
.........\clock.vwf
.........\db\clock.asm.qmsg
.........\..\clock.cbx.xml
.........\..\clock.cmp.cdb
.........\..\clock.cmp.hdb
.........\..\clock.cmp.kpt
.........\..\clock.cmp.logdb
.........\..\clock.cmp.rdb
.........\..\clock.cmp.tdb
.........\..\clock.cmp0.ddb
.........\..\clock.dbp
.........\..\clock.db_info
.........\..\clock.eco.cdb
.........\..\clock.eds_overflow
.........\..\clock.fit.qmsg
.........\..\clock.hier_info
.........\..\clock.hif
.........\..\clock.map.cdb
.........\..\clock.map.hdb
.........\..\clock.map.logdb
.........\..\clock.map.qmsg
.........\..\clock.pre_map.cdb
.........\..\clock.pre_map.hdb
.........\..\clock.psp
.........\..\clock.rpp.qmsg
.........\..\clock.rtlv.hdb
.........\..\clock.rtlv_sg.cdb
.........\..\clock.rtlv_sg_swap.cdb
.........\..\clock.sgate.rvd
.........\..\clock.sgate_sm.rvd
.........\..\clock.sgdiff.cdb
.........\..\clock.sgdiff.hdb
.........\..\clock.signalprobe.cdb
.........\..\clock.sim.hdb
.........\..\clock.sim.qmsg
.........\..\clock.sim.rdb
.........\..\clock.sim.vwf
.........\..\clock.sld_design_entry.sci
.........\..\clock.sld_design_entry_dsc.sci
.........\..\clock.syn_hier_info
.........\..\clock.tan.qmsg
.........\..\wed.zsf
.........\undo_redo.txt
.........\基于VHDL 数字电子钟.ppt
.........\钟+数电课程设计+数字钟+电子钟+源代码+EDA+VHDL.txt
.........\db
EDA电子钟
.........\clock.asm.rpt
.........\clock.done
.........\clock.fit.rpt
.........\clock.fit.smsg
.........\clock.fit.summary
.........\clock.flow.rpt
.........\clock.map.rpt
.........\clock.map.summary
.........\clock.pin
.........\clock.pof
.........\clock.qpf
.........\clock.qsf
.........\clock.qws
.........\clock.sim.rpt
.........\clock.sof
.........\clock.tan.rpt
.........\clock.tan.summary
.........\clock.vhd
.........\clock.vwf
.........\db\clock.asm.qmsg
.........\..\clock.cbx.xml
.........\..\clock.cmp.cdb
.........\..\clock.cmp.hdb
.........\..\clock.cmp.kpt
.........\..\clock.cmp.logdb
.........\..\clock.cmp.rdb
.........\..\clock.cmp.tdb
.........\..\clock.cmp0.ddb
.........\..\clock.dbp
.........\..\clock.db_info
.........\..\clock.eco.cdb
.........\..\clock.eds_overflow
.........\..\clock.fit.qmsg
.........\..\clock.hier_info
.........\..\clock.hif
.........\..\clock.map.cdb
.........\..\clock.map.hdb
.........\..\clock.map.logdb
.........\..\clock.map.qmsg
.........\..\clock.pre_map.cdb
.........\..\clock.pre_map.hdb
.........\..\clock.psp
.........\..\clock.rpp.qmsg
.........\..\clock.rtlv.hdb
.........\..\clock.rtlv_sg.cdb
.........\..\clock.rtlv_sg_swap.cdb
.........\..\clock.sgate.rvd
.........\..\clock.sgate_sm.rvd
.........\..\clock.sgdiff.cdb
.........\..\clock.sgdiff.hdb
.........\..\clock.signalprobe.cdb
.........\..\clock.sim.hdb
.........\..\clock.sim.qmsg
.........\..\clock.sim.rdb
.........\..\clock.sim.vwf
.........\..\clock.sld_design_entry.sci
.........\..\clock.sld_design_entry_dsc.sci
.........\..\clock.syn_hier_info
.........\..\clock.tan.qmsg
.........\..\wed.zsf
.........\undo_redo.txt
.........\基于VHDL 数字电子钟.ppt
.........\钟+数电课程设计+数字钟+电子钟+源代码+EDA+VHDL.txt
.........\db
EDA电子钟