shift_reg

.........\component

.........\constraint

.........\coreconsole

.........\designer

.........\........\impl1

.........\........\.....\designer.log

.........\........\.....\designer_gen_ba.log

.........\........\.....\shift_reg.adb

.........\........\.....\shift_reg.dtf

.........\........\.....\.............\verify.log

.........\........\.....\shift_reg.ide_des

.........\........\.....\shift_reg.pdb

.........\........\.....\shift_reg.pdb.depends

.........\........\.....\shift_reg.tcl

.........\........\.....\shift_reg_ba.sdf

.........\........\.....\shift_reg_ba.sdf_max.csd

.........\........\.....\shift_reg_ba.v

.........\........\.....\shift_reg_fp

.........\........\.....\............\$$FlashPro_FPBBALTLPT1.L$$

.........\........\.....\............\projectData

.........\........\.....\............\...........\shift_reg.pdb

.........\........\.....\............\shift_reg.log

.........\........\.....\............\shift_reg.pro

.........\........\.....\simulation

.........\........\.....\..........\postlayout

.........\........\.....\..........\..........\shift_reg

.........\........\.....\..........\..........\.........\verilog.psm

.........\........\.....\..........\..........\.........\_primary.dat

.........\........\.....\..........\..........\.........\_primary.dbs

.........\........\.....\..........\..........\.........\_primary.vhd

.........\........\.....\..........\..........\_info

.........\........\.....\..........\..........\_temp

.........\........\.....\..........\..........\_vmake

.........\hdl

.........\...\clk_div.v

.........\...\shift_reg.v

.........\phy_synthesis

.........\shift_reg.prj

.........\simulation

.........\..........\modelsim.ini

.........\..........\modelsim.ini.sav

.........\..........\modelsim.log

.........\..........\run.do

.........\..........\vsim.wlf

.........\smartgen

.........\........\smartgen.aws

.........\stimulus

.........\synthesis

.........\.........\.recordref

.........\.........\backup

.........\.........\......\shift_reg.srr

.........\.........\coreip

.........\.........\run_options.txt

.........\.........\shift_reg.areasrr

.........\.........\shift_reg.edn

.........\.........\shift_reg.map

.........\.........\shift_reg.pdc

.........\.........\shift_reg.sdf

.........\.........\shift_reg.so

.........\.........\shift_reg.srd

.........\.........\shift_reg.srm

.........\.........\shift_reg.srr

.........\.........\shift_reg.srs

.........\.........\shift_reg.szr

.........\.........\shift_reg.tlg

.........\.........\shift_reg_sdc.sdc

.........\.........\shift_reg_syn.prj

.........\.........\stdout.log

.........\.........\synthesis_identify

.........\.........\..................\backup

.........\.........\..................\coreip

.........\.........\..................\shift_reg.srs

.........\.........\..................\shift_reg.tlg

.........\.........\..................\syntmp

.........\.........\syntmp

.........\.........\......\shift_reg.plg

.........\.........\traplog.tlg

.........\viewdraw

.........\........\sch

.........\........\sym

.........\........\vf

.........\........\..\project.lst

.........\........\viewdraw.ini

.........\........\wir