文件名称:VHDL_clock
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VHDL数字钟设计程序 设计要求 基本要求： 1、24小时计数显示； 2、具有校时功能（时，分） ； 附加要求： 1、实现闹钟功能（定时，闹响）；--VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (time, alarm sound) -
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下载文件列表
Vhdl2.vhd.bak
Block1.bdf
count12.vhd
count12.vhd.bak
counter2.bsf
counter12.bsf
counter60.bsf
counter60.vhd
counter60.vhd.bak
shizhong.asm.rpt
shizhong.bdf
shizhong.db_import.rpt
shizhong.done
shizhong.dpf
shizhong.eda.rpt
shizhong.fit.rpt
shizhong.fit.smsg
shizhong.fit.summary
shizhong.flow.rpt
shizhong.map.rpt
shizhong.map.summary
shizhong.pin
shizhong.pof
shizhong.qpf
shizhong.qsf
shizhong.qws
shizhong.sdc
shizhong.sim.rpt
shizhong.sof
shizhong.sta.rpt
shizhong.sta.summary
shizhong.tan.rpt
shizhong.tan.summary
shizhong.vwf
shizhong_nativelink_simulation.rpt
undo_redo.txt
Vhdl2.vhd
Block1.bdf
count12.vhd
count12.vhd.bak
counter2.bsf
counter12.bsf
counter60.bsf
counter60.vhd
counter60.vhd.bak
shizhong.asm.rpt
shizhong.bdf
shizhong.db_import.rpt
shizhong.done
shizhong.dpf
shizhong.eda.rpt
shizhong.fit.rpt
shizhong.fit.smsg
shizhong.fit.summary
shizhong.flow.rpt
shizhong.map.rpt
shizhong.map.summary
shizhong.pin
shizhong.pof
shizhong.qpf
shizhong.qsf
shizhong.qws
shizhong.sdc
shizhong.sim.rpt
shizhong.sof
shizhong.sta.rpt
shizhong.sta.summary
shizhong.tan.rpt
shizhong.tan.summary
shizhong.vwf
shizhong_nativelink_simulation.rpt
undo_redo.txt
Vhdl2.vhd