文件名称:pipeline_ADC_PLL
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- 其他嵌入式/单片机内容
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- 2012-11-26
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- 353kb
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- 赵*
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该文档提出了一种应用于开关电容流水线模数转换器的CMoS预运放一锁存比较
器．该比较器采用UMC混合／射频0．18肛m 1P6M P衬底双阱CMOS工艺设计，工作电压为
1．8 V．该比较器的灵敏度为0．215 mV，最大失调电压为12 mV，差分输入动态范围为1．8
V，分辨率为8位，在40 M的工作频率下，功耗仅为24．4 ttW．基于0．18 gm工艺的仿真结
果验证了比较器设计的有效性．-A CMOS preamplifier-latch comparator used in switched··capacitor pipeline analog··to-digital con·-
verter WBS presented．The comparator WaS d髑igned under UMC Mixed．Mode／RF 0．18 btm 1P6M P．Sub Twin—
Well CMOS process and worked with 1．8V power supply．The sensitivity of the comparator was 0．215 mV，
the largest offset voltage was 12 mV，the differentiaI input range Was 1．8 V，the resolution was 8 bit and the
power dissipation Was only 24．4 gW at 40 MHz．HSPICE simulations of the comparator implemented in a 0．18
um technology demonstrate its effectiveness．
器．该比较器采用UMC混合／射频0．18肛m 1P6M P衬底双阱CMOS工艺设计，工作电压为
1．8 V．该比较器的灵敏度为0．215 mV，最大失调电压为12 mV，差分输入动态范围为1．8
V，分辨率为8位，在40 M的工作频率下，功耗仅为24．4 ttW．基于0．18 gm工艺的仿真结
果验证了比较器设计的有效性．-A CMOS preamplifier-latch comparator used in switched··capacitor pipeline analog··to-digital con·-
verter WBS presented．The comparator WaS d髑igned under UMC Mixed．Mode／RF 0．18 btm 1P6M P．Sub Twin—
Well CMOS process and worked with 1．8V power supply．The sensitivity of the comparator was 0．215 mV，
the largest offset voltage was 12 mV，the differentiaI input range Was 1．8 V，the resolution was 8 bit and the
power dissipation Was only 24．4 gW at 40 MHz．HSPICE simulations of the comparator implemented in a 0．18
um technology demonstrate its effectiveness．
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