文件名称:Advanced_Verilog_Design
介绍说明--下载内容均来自于网络,请自行研究使用
以Lattice 器伴为例,描述如何在Verilog中指定管脚属饪功能(OE,RESET,IO CELL寄存器,双向IO,Latch IO,管脚Pin number, synthesis属性,输出电气规格...),状态机的使用,及其它Verilog进阶功能-With Lattice devices for example, it describes how to specify the pin function in Verilog (OE, RESET, IO CELL register, bi-directional IO, Latch IO, assign Pin number, synthesis properties, the output electrical specifications ...), using State Machine, and other advanced features of Verilog.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Advanced Verilog Design.pdf