文件名称:lab11

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  • 2012-11-26
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所以這次的實驗,就是要設計一組像這樣的裝置,稱之為字串 處理 器。

像這樣,將一個具有特殊功能、須不 斷重覆使用的小電路 ,從主體中分離 出

來 ,讓設計本身更 單純的概念 ,-So this experiment is to design a device like this, called the word串 handling device. Like this will be a special function to be not broken re-use a small circuit, from the main carve out the future leave, so that the design concept itself is more simple,
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下载文件列表

lab11\9312067\Lab11\automake.log

.....\.......\.....\bitgen.ut

.....\.......\.....\Lab11.dhp

.....\.......\.....\Lab11.npl

.....\.......\.....\strproc.vhd

.....\.......\.....\str_test.bgn

.....\.......\.....\str_test.bit

.....\.......\.....\str_test.bld

.....\.......\.....\str_test.cmd_log

.....\.......\.....\str_test.drc

.....\.......\.....\str_test.lso

.....\.......\.....\str_test.mrp

.....\.......\.....\str_test.nc1

.....\.......\.....\str_test.ncd

.....\.......\.....\str_test.ngc

.....\.......\.....\str_test.ngd

.....\.......\.....\str_test.ngm

.....\.......\.....\str_test.ngr

.....\.......\.....\str_test.pad

.....\.......\.....\str_test.pad_txt

.....\.......\.....\str_test.par

.....\.......\.....\str_test.pcf

.....\.......\.....\str_test.placed_ncd_tracker

.....\.......\.....\str_test.prj

.....\.......\.....\str_test.routed_ncd_tracker

.....\.......\.....\str_test.stx

.....\.......\.....\str_test.syr

.....\.......\.....\str_test.twr

.....\.......\.....\str_test.twx

.....\.......\.....\str_test.ucf

.....\.......\.....\str_test.ucf.untf

.....\.......\.....\str_test.ut

.....\.......\.....\str_test.vhd

.....\.......\.....\str_test.xpi

.....\.......\.....\str_test_last_par.ncd

.....\.......\.....\str_test_map.ncd

.....\.......\.....\str_test_map.ngm

.....\.......\.....\str_test_pad.csv

.....\.......\.....\str_test_pad.txt

.....\.......\.....\tx_rx_sp_pkg.vhd

.....\.......\.....\xst\work\hdllib.ref

.....\.......\.....\...\....\hdpdeps.ref

.....\.......\.....\...\....\sub00\vhpl00.vho

.....\.......\.....\...\....\.....\vhpl01.vho

.....\.......\.....\...\....\.....\vhpl02.vho

.....\.......\.....\...\....\.....\vhpl03.vho

.....\.......\.....\...\....\.....\vhpl04.vho

.....\.......\.....\...\....\.....\vhpl05.vho

.....\.......\.....\...\....\.....\vhpl06.vho

.....\.......\.....\...\....\.....\vhpl07.vho

.....\.......\.....\...\....\.....\vhpl08.vho

.....\.......\.....\...\....\.....\vhpl09.vho

.....\.......\.....\...\....\.....\vhpl10.vho

.....\.......\.....\...\....\.....\vhpl11.vho

.....\.......\.....\...\....\.....\vhpl12.vho

.....\.......\.....\...\....\.....\vhpl13.vho

.....\.......\.....\...\....\.....\vhpl14.vho

.....\.......\.....\...\....\.....\vhpl15.vho

.....\.......\.....\...\....\.....\vhpl16.vho

.....\.......\.....\...\....\.....\vhpl17.vho

.....\.......\.....\...\....\.....\vhpl18.vho

.....\.......\.....\...\....\.....\vhpl19.vho

.....\.......\.....\...\....\.....\vhpl20.vho

.....\.......\.....\...\....\.....\vhpl21.vho

.....\.......\.....\_impact.cmd

.....\.......\.....\_impact.log

.....\.......\.....\.ngo\netlist.lst

.....\.......\.....\._projnav\bitgen.rsp

.....\.......\.....\.........\ednTOngd_tcl.rsp

.....\.......\.....\.........\Lab11.gfl

.....\.......\.....\.........\Lab11_flowplus.gfl

.....\.......\.....\.........\map.log

.....\.......\.....\.........\nc1TOncd_tcl.rsp

.....\.......\.....\.........\par.log

.....\.......\.....\.........\posttrc.log

.....\.......\.....\.........\runXst_tcl.rsp

.....\.......\.....\.........\str_test.xst

.....\.......\.....\.........\str_test_ncdTOut_tcl.rsp

.....\.......\.....\__projnav.log

.....\FPGA lab11實驗報告.doc

.....\Lab11-subblock_design_1.pdf

.....\lab117788\Lab11-subblock_design_1.pdf

.....\.........\strproc.vhd

.....\.........\str_test.ucf

.....\.........\str_test.vhd

.....\.........\tx_rx_sp_pkg.vhd

.....\strproc.vhd

.....\str_test.ucf

.....\str_test.vhd

.....\tx_rx_sp_pkg.vhd

.....\9312067\Lab11\xst\work\sub00

.....\.......\.....\...\work

.....\.......\.....\xst

.....\.......\.....\_ngo

.....\.......\.....\__projnav

.....\.......\Lab11

.....\9312067

.....\lab117788

lab11

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