文件名称:sdram_ver_134
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This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory.
This code is based Xilinx FPGA Playform.
This code is based Xilinx FPGA Playform.
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VHDL
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(系统自动生成,下载前可以参看下载内容)
下载文件列表
sdram_ver_134\brst_cntr.v
.............\cslt_cntr.v
.............\define.v
.............\ki_cntr.v
.............\rcd_cntr.v
.............\ref_cntr.v
.............\sdrmc_state.v
.............\sdrm_t.v
.............\sdrm.v
.............\string_decode_fn.v
.............\string_decode_post_route.v
.............\sys_int.v
.............\sdrm.ucf
.............\sdram_ver_134.ise
.............\readme
.............\tb_post_route.tf
.............\tb_sdrm.tf
.............\micron\mt48lc1m16a1-8a.v
.............\......\mt48lc1m16a1.v
.............\......\test.v
.............\......\bank0.txt
.............\......\bank1.txt
.............\cslt_cntr.v
.............\define.v
.............\ki_cntr.v
.............\rcd_cntr.v
.............\ref_cntr.v
.............\sdrmc_state.v
.............\sdrm_t.v
.............\sdrm.v
.............\string_decode_fn.v
.............\string_decode_post_route.v
.............\sys_int.v
.............\sdrm.ucf
.............\sdram_ver_134.ise
.............\readme
.............\tb_post_route.tf
.............\tb_sdrm.tf
.............\micron\mt48lc1m16a1-8a.v
.............\......\mt48lc1m16a1.v
.............\......\test.v
.............\......\bank0.txt
.............\......\bank1.txt