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文件名称:sva_labs_public

  • 所属分类：
  • 书籍源码
  • 资源属性：
  • [VHDL] [源码]
  • 上传时间：
  • 2012-11-26
  • 文件大小：
  • 176kb
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  • 0次
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  • 即*
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system verilog这是一本关于verilog编程语言的教程,对学习verilog语言有帮助-system verilog
(系统自动生成,下载前可以参看下载内容)

下载文件列表

sva_labs_public

...............\Labs

...............\....\1_Lab

...............\....\.....\Makefile

...............\....\2_Lab

...............\....\.....\aep_dir

...............\....\.....\.......\aep.cfg

...............\....\.....\.......\aep.prj

...............\....\.....\.......\wb_dma_rf.v

...............\....\.....\dma_engine.sva

...............\....\.....\Makefile

...............\....\.....\README

...............\....\.....\solutions

...............\....\.....\.........\aep.cfg

...............\....\.....\.........\aep.prj

...............\....\.....\.........\dma_engine.sva

...............\....\3_Lab

...............\....\.....\dma_engine.sva

...............\....\.....\Makefile

...............\....\.....\README

...............\....\.....\solutions

...............\....\.....\.........\#wb_int.sva#

...............\....\.....\.........\dma_engine.sva

...............\....\.....\.........\wb_int.sva

...............\....\.....\wb_int.sva

...............\....\4_Lab

...............\....\.....\dma_engine.sva

...............\....\.....\Makefile

...............\....\.....\README

...............\....\.....\solutions

...............\....\.....\.........\dma_engine.sva

...............\....\.....\.........\wb_int.sva

...............\....\.....\wb_int.sva

...............\....\5_Lab

...............\....\.....\dma_engine.sva

...............\....\.....\Makefile

...............\....\.....\README

...............\....\.....\simv.vdb

...............\....\.....\........\.assertDeclInfo

...............\....\.....\........\fcov

...............\....\.....\........\....\results.db

...............\....\.....\........\reports

...............\....\.....\........\.......\report.fcov

...............\....\.....\........\.......\...........\category.html

...............\....\.....\........\.......\...........\hier.html

...............\....\.....\........\.......\...........\tests.html

...............\....\.....\........\.......\report.index.html

...............\....\.....\solutions

...............\....\.....\.........\dma_engine.sva

...............\....\.....\.........\report.index.html

...............\....\.....\.........\wb_int.sva

...............\....\.....\wb_int.sva

...............\....\6_Lab

...............\....\.....\proj_dir

...............\....\.....\........\coverage.prj

...............\....\.....\........\dma.prj

...............\....\.....\........\dma_fail.prj

...............\....\.....\........\dma_step_1.tcl

...............\....\.....\........\dma_step_3.tcl

...............\....\.....\........\sfail.cfg

...............\....\.....\........\sfail_session.tcl

...............\....\.....\........\wb_dma_de.v

...............\....\.....\solutions

...............\....\.....\.........\coverage.prj

...............\....\.....\.........\dma.prj

...............\....\.....\.........\dma.tcl

...............\....\.....\.........\dma_fail.prj

...............\....\.....\.........\dma_step_1.tcl

...............\....\.....\.........\dma_step_3.tcl

...............\....\.....\.........\magellan_results.log

...............\....\.....\.........\sfail.cfg

...............\....\.....\sva_dir

...............\....\.....\.......\dma_engine.sva

...............\....\.....\.......\DMA_Engine_Constraints.sva

...............\....\.....\.......\wb_int.sva

...............\....\.....\.......\Wb_Interface_Constraints.sva

...............\wb_dma

...............\......\bench

...............\......\.....\CVS

...............\......\.....\...\Entries

...............\......\.....\...\Repository

...............\......\.....\...\Root

...............\......\.....\verilog

...............\......\.....\.......\CVS

...............\......\.....\.......\...\Entries

...............\......\.....\.......\...\Repository

...............\......\.....\.......\...\Root

...............\......\.....\.......\tests.v

...............\......\.....\.......\test_bench_top.v

...............\......\.....\.......\test_bench_top.v.old

...............\......\.....\.......\wb_mast_model.v

...............\......\.....\.......\wb_model_defines.v

...............\......\.....\.......\wb_slv_model.v

...............\..

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