文件名称:ADC0809VHDL
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8.4 ADC0809 VHDL控制程序
见随书所附光盘中文件：ADC0809VHDL程序与仿真。
--文件名：ADC0809.vhd
--功能：基于VHDL语言，实现对ADC0809简单控制
--说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系
--统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。
--最后修改日期：2004.3.20
-8.4 ADC0809 VHDL control procedures, see the book with accompanying CD-ROM in the file: ADC0809VHDL procedures and simulation.- File Name: ADC0809.vhd- features: Based on the VHDL language, to achieve a simple control ADC0809- Descr iption: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock signal, here by the Department of FPGA- EC clock (50MHz ) by the 256 sub-frequency has been clk1 (195KHz) as ADC0809 clock conversion work.- Last modified date: 2004.3.20
见随书所附光盘中文件：ADC0809VHDL程序与仿真。
--文件名：ADC0809.vhd
--功能：基于VHDL语言，实现对ADC0809简单控制
--说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系
--统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。
--最后修改日期：2004.3.20
-8.4 ADC0809 VHDL control procedures, see the book with accompanying CD-ROM in the file: ADC0809VHDL procedures and simulation.- File Name: ADC0809.vhd- features: Based on the VHDL language, to achieve a simple control ADC0809- Descr iption: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock signal, here by the Department of FPGA- EC clock (50MHz ) by the 256 sub-frequency has been clk1 (195KHz) as ADC0809 clock conversion work.- Last modified date: 2004.3.20
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ADC0809VHDL.doc