文件名称:statemechine
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1kb
- 下载次数：
- 0次
- 提 供 者：
- dhana*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
We are using parameters is the test bench and passing them to the state machine using parameter passing
We are using tasks to control the flow of the testbench
We are using hierarchical naming to access the state variable in the state machine from the test bench.
Finally we are using test bench messages which allow us to monitor the current state from the simulation waveform viewer (assuming we change the bus radix of the message to ascii.
-We are using parameters is the test bench and passing them to the state machine using parameter passing
We are using tasks to control the flow of the testbench
We are using hierarchical naming to access the state variable in the state machine from the test bench.
Finally we are using test bench messages which allow us to monitor the current state from the simulation waveform viewer (assuming we change the bus radix of the message to ascii.
We are using tasks to control the flow of the testbench
We are using hierarchical naming to access the state variable in the state machine from the test bench.
Finally we are using test bench messages which allow us to monitor the current state from the simulation waveform viewer (assuming we change the bus radix of the message to ascii.
-We are using parameters is the test bench and passing them to the state machine using parameter passing
We are using tasks to control the flow of the testbench
We are using hierarchical naming to access the state variable in the state machine from the test bench.
Finally we are using test bench messages which allow us to monitor the current state from the simulation waveform viewer (assuming we change the bus radix of the message to ascii.
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下载文件列表
statemechine\statemechne.v
statemechine
statemechine