文件名称:tut_timing_verilog
- 所属分类：
- VHDL编程
- 资源属性：
- [PDF]
- 上传时间：
- 2012-11-26
- 文件大小：
- 361kb
- 下载次数：
- 0次
- 提 供 者：
- Nguyen ********
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
Verilog source code is usually typed into one or more text files on a
computer. Those text files are then submitted to a Verilog compiler
or interpreter which builds the data files necessary for simulation or
synthesis. Sometimes simulation immediately follows compilation
with no intermediate data files being created.
computer. Those text files are then submitted to a Verilog compiler
or interpreter which builds the data files necessary for simulation or
synthesis. Sometimes simulation immediately follows compilation
with no intermediate data files being created.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
tut_timing_verilog.pdf