文件名称:tut_quartus_intro_verilog
- 所属分类：
- VHDL编程
- 资源属性：
- [PDF]
- 上传时间：
- 2012-11-26
- 文件大小：
- 800kb
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- 0次
- 提 供 者：
- Nguyen ********
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Verilog source code is usually typed into one or more text files on a
computer. Those text files are then submitted to a Verilog compiler
or interpreter which builds the data files necessary for simulation or
synthesis. Sometimes simulation immediately follows compilation
with no intermediate data files being created.
computer. Those text files are then submitted to a Verilog compiler
or interpreter which builds the data files necessary for simulation or
synthesis. Sometimes simulation immediately follows compilation
with no intermediate data files being created.
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tut_quartus_intro_verilog.pdf