文件名称:edaok_UART_FPGA
介绍说明－－下载内容均来自于网络，请自行研究使用
用FPGA实现UART的串口通信，可以设置数据位，校验位，奇偶校验等-With the FPGA to achieve UART serial communication, you can set the data bits, parity bit, parity, etc.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
edaok_UART的FPGA设计文档\读我.txt
........................\UART设计文档.pdf
........................\fpga\V0p10\uart.qpf
........................\....\.....\uart.qsf
........................\....\.....\uart_description.txt
........................\....\.....\uart.map.smsg
........................\....\.....\uart.map.summary
........................\....\.....\uart.pin
........................\....\.....\uart.fit.smsg
........................\....\.....\uart.fit.summary
........................\....\.....\uart.sof
........................\....\.....\uart.pof
........................\....\.....\uart.tan.summary
........................\....\.....\uart.done
........................\....\.....\uart.dpf
........................\....\.....\uart.cdf
........................\....\.....\top.bsf
........................\....\.....\src\txd.v
........................\....\.....\...\uart.v
........................\....\.....\...\divider.v
........................\....\.....\...\ebi.v
........................\....\.....\...\rxd.v
........................\....\.....\...\top.v
........................\....\.....\testbench\vsim_stacktrace.vstf
........................\....\.....\.........\transcript
........................\....\.....\.........\vish_stacktrace.vstf
........................\....\.....\.........\top_tb.v
........................\....\.....\.........\ModelSim.jpg
........................\....\.....\.........\tcl_stacktrace.txt
........................\....\.....\.........\vsim.wlf
........................\....\.....\.........\uart.mpf
........................\....\.....\.........\uart.cr.mti
........................\....\.....\.........\cycloneII_v\_info
........................\....\.....\.........\work\_info
........................\....\.....\.........\....\uart\_primary.vhd
........................\....\.....\.........\....\....\_primary.dat
........................\....\.....\.........\....\....\verilog.asm
........................\....\.....\.........\....\rxd\_primary.vhd
........................\....\.....\.........\....\...\_primary.dat
........................\....\.....\.........\....\...\verilog.asm
........................\....\.....\.........\....\txd\_primary.vhd
........................\....\.....\.........\....\...\_primary.dat
........................\....\.....\.........\....\...\verilog.asm
........................\....\.....\.........\....\.op\_primary.vhd
........................\....\.....\.........\....\...\_primary.dat
........................\....\.....\.........\....\...\verilog.asm
........................\....\.....\.........\....\ebi\_primary.vhd
........................\....\.....\.........\....\...\_primary.dat
........................\....\.....\.........\....\...\verilog.asm
........................\....\.....\.........\....\division\_primary.vhd
........................\....\.....\.........\....\........\_primary.dat
........................\....\.....\.........\....\........\verilog.asm
........................\....\.....\.........\....\....der\_primary.vhd
........................\....\.....\.........\....\.......\_primary.dat
........................\....\.....\.........\....\.......\verilog.asm
........................\....\.....\.........\....\top_tb\_primary.vhd
........................\....\.....\.........\....\......\_primary.dat
........................\....\.....\.........\....\......\verilog.asm
........................\....\.....\uart.map.rpt
........................\....\.....\uart.fit.rpt
........................\....\.....\uart.asm.rpt
........................\....\.....\uart.tan.rpt
........................\....\.....\uart.flow.rpt
........................\....\.....\uart.qws
........................\Mcu\UartTest\stdinc.h
........................\...\........\UartCtrl.c
........................\...\........\UartTest.eww
........................\...\........\UartTest.ewp
........................\...\........\UartTest.ewd
........................\...\........\UartTest.dep
........................\...\........\main.c
........................\...\........\FpgaInc.h
............
........................\UART设计文档.pdf
........................\fpga\V0p10\uart.qpf
........................\....\.....\uart.qsf
........................\....\.....\uart_description.txt
........................\....\.....\uart.map.smsg
........................\....\.....\uart.map.summary
........................\....\.....\uart.pin
........................\....\.....\uart.fit.smsg
........................\....\.....\uart.fit.summary
........................\....\.....\uart.sof
........................\....\.....\uart.pof
........................\....\.....\uart.tan.summary
........................\....\.....\uart.done
........................\....\.....\uart.dpf
........................\....\.....\uart.cdf
........................\....\.....\top.bsf
........................\....\.....\src\txd.v
........................\....\.....\...\uart.v
........................\....\.....\...\divider.v
........................\....\.....\...\ebi.v
........................\....\.....\...\rxd.v
........................\....\.....\...\top.v
........................\....\.....\testbench\vsim_stacktrace.vstf
........................\....\.....\.........\transcript
........................\....\.....\.........\vish_stacktrace.vstf
........................\....\.....\.........\top_tb.v
........................\....\.....\.........\ModelSim.jpg
........................\....\.....\.........\tcl_stacktrace.txt
........................\....\.....\.........\vsim.wlf
........................\....\.....\.........\uart.mpf
........................\....\.....\.........\uart.cr.mti
........................\....\.....\.........\cycloneII_v\_info
........................\....\.....\.........\work\_info
........................\....\.....\.........\....\uart\_primary.vhd
........................\....\.....\.........\....\....\_primary.dat
........................\....\.....\.........\....\....\verilog.asm
........................\....\.....\.........\....\rxd\_primary.vhd
........................\....\.....\.........\....\...\_primary.dat
........................\....\.....\.........\....\...\verilog.asm
........................\....\.....\.........\....\txd\_primary.vhd
........................\....\.....\.........\....\...\_primary.dat
........................\....\.....\.........\....\...\verilog.asm
........................\....\.....\.........\....\.op\_primary.vhd
........................\....\.....\.........\....\...\_primary.dat
........................\....\.....\.........\....\...\verilog.asm
........................\....\.....\.........\....\ebi\_primary.vhd
........................\....\.....\.........\....\...\_primary.dat
........................\....\.....\.........\....\...\verilog.asm
........................\....\.....\.........\....\division\_primary.vhd
........................\....\.....\.........\....\........\_primary.dat
........................\....\.....\.........\....\........\verilog.asm
........................\....\.....\.........\....\....der\_primary.vhd
........................\....\.....\.........\....\.......\_primary.dat
........................\....\.....\.........\....\.......\verilog.asm
........................\....\.....\.........\....\top_tb\_primary.vhd
........................\....\.....\.........\....\......\_primary.dat
........................\....\.....\.........\....\......\verilog.asm
........................\....\.....\uart.map.rpt
........................\....\.....\uart.fit.rpt
........................\....\.....\uart.asm.rpt
........................\....\.....\uart.tan.rpt
........................\....\.....\uart.flow.rpt
........................\....\.....\uart.qws
........................\Mcu\UartTest\stdinc.h
........................\...\........\UartCtrl.c
........................\...\........\UartTest.eww
........................\...\........\UartTest.ewp
........................\...\........\UartTest.ewd
........................\...\........\UartTest.dep
........................\...\........\main.c
........................\...\........\FpgaInc.h
............