文件名称:FPGA_Clk
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1.4mb
- 下载次数：
- 0次
- 提 供 者：
- icemo******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。
使用计时器的方式产生时钟波形。
提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.
使用计时器的方式产生时钟波形。
提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.
相关搜索： FPGA
timer
vhdl
clock
generator
clock
signal
in
fpga
FPGA
时钟
clock
generator
vhdl
cyclone
FPGA
产生
脉冲
波形
VHDL
Generator
timer
vhdl
clock
generator
clock
signal
in
fpga
FPGA
时钟
clock
generator
vhdl
cyclone
FPGA
产生
脉冲
波形
VHDL
Generator
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA_Clk\db\add_sub_8rh.tdf
........\..\altsyncram_kso3.tdf
........\..\altsyncram_qso3.tdf
........\..\cmpr_j4c.tdf
........\..\cmpr_l4c.tdf
........\..\cmpr_n4c.tdf
........\..\cntr_a4i.tdf
........\..\cntr_c4i.tdf
........\..\cntr_cti.tdf
........\..\cntr_iti.tdf
........\..\cntr_p2i.tdf
........\..\cntr_umi.tdf
........\..\decode_9jf.tdf
........\..\FPGA_Clk.asm.qmsg
........\..\FPGA_Clk.cbx.xml
........\..\FPGA_Clk.cmp.bpm
........\..\FPGA_Clk.cmp.cdb
........\..\FPGA_Clk.cmp.ecobp
........\..\FPGA_Clk.cmp.hdb
........\..\FPGA_Clk.cmp.kpt
........\..\FPGA_Clk.cmp.logdb
........\..\FPGA_Clk.cmp.rdb
........\..\FPGA_Clk.cmp.tdb
........\..\FPGA_Clk.cmp0.ddb
........\..\FPGA_Clk.cmp_merge.kpt
........\..\FPGA_Clk.db_info
........\..\FPGA_Clk.eco.cdb
........\..\FPGA_Clk.eds_overflow
........\..\FPGA_Clk.fit.qmsg
........\..\FPGA_Clk.fnsim.hdb
........\..\FPGA_Clk.fnsim.qmsg
........\..\FPGA_Clk.hier_info
........\..\FPGA_Clk.hif
........\..\FPGA_Clk.lpc.html
........\..\FPGA_Clk.lpc.rdb
........\..\FPGA_Clk.lpc.txt
........\..\FPGA_Clk.map.bpm
........\..\FPGA_Clk.map.cdb
........\..\FPGA_Clk.map.ecobp
........\..\FPGA_Clk.map.hdb
........\..\FPGA_Clk.map.kpt
........\..\FPGA_Clk.map.logdb
........\..\FPGA_Clk.map.qmsg
........\..\FPGA_Clk.map_bb.cdb
........\..\FPGA_Clk.map_bb.hdb
........\..\FPGA_Clk.map_bb.logdb
........\..\FPGA_Clk.pre_map.cdb
........\..\FPGA_Clk.pre_map.hdb
........\..\FPGA_Clk.rtlv.hdb
........\..\FPGA_Clk.rtlv_sg.cdb
........\..\FPGA_Clk.rtlv_sg_swap.cdb
........\..\FPGA_Clk.sgdiff.cdb
........\..\FPGA_Clk.sgdiff.hdb
........\..\FPGA_Clk.sim.cvwf
........\..\FPGA_Clk.sim.hdb
........\..\FPGA_Clk.sim.qmsg
........\..\FPGA_Clk.sim.rdb
........\..\FPGA_Clk.simfam
........\..\FPGA_Clk.sld_design_entry.sci
........\..\FPGA_Clk.sld_design_entry_dsc.sci
........\..\FPGA_Clk.smp_dump.txt
........\..\FPGA_Clk.syn_hier_info
........\..\FPGA_Clk.tan.qmsg
........\..\FPGA_Clk.tis_db_list.ddb
........\..\FPGA_Clk_global_asgn_op.abo
........\..\mux_ngc.tdf
........\..\mux_pgc.tdf
........\..\prev_cmp_FPGA_Clk.asm.qmsg
........\..\prev_cmp_FPGA_Clk.fit.qmsg
........\..\prev_cmp_FPGA_Clk.map.qmsg
........\..\prev_cmp_FPGA_Clk.qmsg
........\..\prev_cmp_FPGA_Clk.sim.qmsg
........\..\prev_cmp_FPGA_Clk.tan.qmsg
........\..\wed.wsf
........\FPGA_Clk.asm.rpt
........\FPGA_Clk.bsf
........\FPGA_Clk.done
........\FPGA_Clk.dpf
........\FPGA_Clk.fit.rpt
........\FPGA_Clk.fit.smsg
........\FPGA_Clk.fit.summary
........\FPGA_Clk.flow.rpt
........\FPGA_Clk.jdi
........\FPGA_Clk.map.rpt
........\FPGA_Clk.map.smsg
........\FPGA_Clk.map.summary
........\FPGA_Clk.pin
........\FPGA_Clk.pof
........\FPGA_Clk.qpf
........\FPGA_Clk.qsf
........\FPGA_Clk.qws
........\FPGA_Clk.sim.rpt
........\FPGA_Clk.sof
........\FPGA_Clk.tan.rpt
........\FPGA_Clk.tan.summary
........\FPGA_Clk.v
........\FPGA_Clk.v.bak
........\FPGA_Clk.vwf
........\incremental_db\compiled_partitions\FPGA_Clk.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
........\..............\...................\FPGA_Clk.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.hdbx
........\..\altsyncram_kso3.tdf
........\..\altsyncram_qso3.tdf
........\..\cmpr_j4c.tdf
........\..\cmpr_l4c.tdf
........\..\cmpr_n4c.tdf
........\..\cntr_a4i.tdf
........\..\cntr_c4i.tdf
........\..\cntr_cti.tdf
........\..\cntr_iti.tdf
........\..\cntr_p2i.tdf
........\..\cntr_umi.tdf
........\..\decode_9jf.tdf
........\..\FPGA_Clk.asm.qmsg
........\..\FPGA_Clk.cbx.xml
........\..\FPGA_Clk.cmp.bpm
........\..\FPGA_Clk.cmp.cdb
........\..\FPGA_Clk.cmp.ecobp
........\..\FPGA_Clk.cmp.hdb
........\..\FPGA_Clk.cmp.kpt
........\..\FPGA_Clk.cmp.logdb
........\..\FPGA_Clk.cmp.rdb
........\..\FPGA_Clk.cmp.tdb
........\..\FPGA_Clk.cmp0.ddb
........\..\FPGA_Clk.cmp_merge.kpt
........\..\FPGA_Clk.db_info
........\..\FPGA_Clk.eco.cdb
........\..\FPGA_Clk.eds_overflow
........\..\FPGA_Clk.fit.qmsg
........\..\FPGA_Clk.fnsim.hdb
........\..\FPGA_Clk.fnsim.qmsg
........\..\FPGA_Clk.hier_info
........\..\FPGA_Clk.hif
........\..\FPGA_Clk.lpc.html
........\..\FPGA_Clk.lpc.rdb
........\..\FPGA_Clk.lpc.txt
........\..\FPGA_Clk.map.bpm
........\..\FPGA_Clk.map.cdb
........\..\FPGA_Clk.map.ecobp
........\..\FPGA_Clk.map.hdb
........\..\FPGA_Clk.map.kpt
........\..\FPGA_Clk.map.logdb
........\..\FPGA_Clk.map.qmsg
........\..\FPGA_Clk.map_bb.cdb
........\..\FPGA_Clk.map_bb.hdb
........\..\FPGA_Clk.map_bb.logdb
........\..\FPGA_Clk.pre_map.cdb
........\..\FPGA_Clk.pre_map.hdb
........\..\FPGA_Clk.rtlv.hdb
........\..\FPGA_Clk.rtlv_sg.cdb
........\..\FPGA_Clk.rtlv_sg_swap.cdb
........\..\FPGA_Clk.sgdiff.cdb
........\..\FPGA_Clk.sgdiff.hdb
........\..\FPGA_Clk.sim.cvwf
........\..\FPGA_Clk.sim.hdb
........\..\FPGA_Clk.sim.qmsg
........\..\FPGA_Clk.sim.rdb
........\..\FPGA_Clk.simfam
........\..\FPGA_Clk.sld_design_entry.sci
........\..\FPGA_Clk.sld_design_entry_dsc.sci
........\..\FPGA_Clk.smp_dump.txt
........\..\FPGA_Clk.syn_hier_info
........\..\FPGA_Clk.tan.qmsg
........\..\FPGA_Clk.tis_db_list.ddb
........\..\FPGA_Clk_global_asgn_op.abo
........\..\mux_ngc.tdf
........\..\mux_pgc.tdf
........\..\prev_cmp_FPGA_Clk.asm.qmsg
........\..\prev_cmp_FPGA_Clk.fit.qmsg
........\..\prev_cmp_FPGA_Clk.map.qmsg
........\..\prev_cmp_FPGA_Clk.qmsg
........\..\prev_cmp_FPGA_Clk.sim.qmsg
........\..\prev_cmp_FPGA_Clk.tan.qmsg
........\..\wed.wsf
........\FPGA_Clk.asm.rpt
........\FPGA_Clk.bsf
........\FPGA_Clk.done
........\FPGA_Clk.dpf
........\FPGA_Clk.fit.rpt
........\FPGA_Clk.fit.smsg
........\FPGA_Clk.fit.summary
........\FPGA_Clk.flow.rpt
........\FPGA_Clk.jdi
........\FPGA_Clk.map.rpt
........\FPGA_Clk.map.smsg
........\FPGA_Clk.map.summary
........\FPGA_Clk.pin
........\FPGA_Clk.pof
........\FPGA_Clk.qpf
........\FPGA_Clk.qsf
........\FPGA_Clk.qws
........\FPGA_Clk.sim.rpt
........\FPGA_Clk.sof
........\FPGA_Clk.tan.rpt
........\FPGA_Clk.tan.summary
........\FPGA_Clk.v
........\FPGA_Clk.v.bak
........\FPGA_Clk.vwf
........\incremental_db\compiled_partitions\FPGA_Clk.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
........\..............\...................\FPGA_Clk.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.hdbx