文件名称:altera_up_avalon_vga
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VGA altera官方例程Verilog代码 详细说明很好很实用-VGA altera detailed descr iption of the official routine Verilog code for a very good very practical
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下载文件列表
altera_up_avalon_vga\Altera_UP_Avalon_VGA_hw.tcl
....................\Altera_UP_VGA_Color.v
....................\Altera_UP_VGA_Timing.v
....................\class.ptf
....................\doc\ADV7123_a.pdf
....................\...\Altera_UP_Avalon_VGA.pdf
....................\...\VGA.pdf
....................\HAL\inc\altera_up_avalon_vga.h
....................\...\src\altera_up_avalon_vga.c
....................\...\...\component.mk
....................\hdl\Altera_UP_128_Character_Rom.v
....................\...\Altera_UP_Avalon_SRAM.v
....................\...\Altera_UP_Avalon_VGA.v
....................\...\Altera_UP_Character_Buffer.v
....................\...\Altera_UP_FB_Color_Rom.v
....................\...\Altera_UP_Pixel_Buffer.v
....................\...\Altera_UP_VGA_DAC.v
....................\...\Char_Mode_Rom_128.mif
....................\...\FB_Color_Rom.mif
....................\inc\altera_up_avalon_vga_regs.h
....................\testbench\Altera_UP_VGA_DAC.v
....................\.........\Pixel_Test.cr.mti
....................\.........\Pixel_Test.mpf
....................\.........\pixel_testbench.v
....................\.........\tb.tcl
....................\.........\vga.v
....................\.........\vsim.wlf
....................\.........\w.do
....................\.........\.ork\@altera_@u@p_@v@g@a_@d@a@c\verilog.psm
....................\.........\....\..........................\_primary.dat
....................\.........\....\..........................\_primary.vhd
....................\.........\....\pixel_testbench\verilog.psm
....................\.........\....\...............\_primary.dat
....................\.........\....\...............\_primary.vhd
....................\.........\....\testbench\verilog.psm
....................\.........\....\.........\_primary.dat
....................\.........\....\.........\_primary.vhd
....................\.........\....\vga\verilog.psm
....................\.........\....\...\_primary.dat
....................\.........\....\...\_primary.vhd
....................\.........\....\_info
....................\UP_Argument_Parser.pm
....................\UP_Extras.pm
....................\UP_HDL_Parser.pm
....................\UP_HDL_Writer.pm
....................\UP_IP_Core_Generator.pl
....................\UP_PTF_Parser.pm
....................\UP_System_Info.pm
....................\testbench\work\@altera_@u@p_@v@g@a_@d@a@c
....................\.........\....\pixel_testbench
....................\.........\....\testbench
....................\.........\....\vga
....................\HAL\inc
....................\...\src
....................\testbench\work
....................\doc
....................\HAL
....................\hdl
....................\inc
....................\testbench
altera_up_avalon_vga
....................\Altera_UP_VGA_Color.v
....................\Altera_UP_VGA_Timing.v
....................\class.ptf
....................\doc\ADV7123_a.pdf
....................\...\Altera_UP_Avalon_VGA.pdf
....................\...\VGA.pdf
....................\HAL\inc\altera_up_avalon_vga.h
....................\...\src\altera_up_avalon_vga.c
....................\...\...\component.mk
....................\hdl\Altera_UP_128_Character_Rom.v
....................\...\Altera_UP_Avalon_SRAM.v
....................\...\Altera_UP_Avalon_VGA.v
....................\...\Altera_UP_Character_Buffer.v
....................\...\Altera_UP_FB_Color_Rom.v
....................\...\Altera_UP_Pixel_Buffer.v
....................\...\Altera_UP_VGA_DAC.v
....................\...\Char_Mode_Rom_128.mif
....................\...\FB_Color_Rom.mif
....................\inc\altera_up_avalon_vga_regs.h
....................\testbench\Altera_UP_VGA_DAC.v
....................\.........\Pixel_Test.cr.mti
....................\.........\Pixel_Test.mpf
....................\.........\pixel_testbench.v
....................\.........\tb.tcl
....................\.........\vga.v
....................\.........\vsim.wlf
....................\.........\w.do
....................\.........\.ork\@altera_@u@p_@v@g@a_@d@a@c\verilog.psm
....................\.........\....\..........................\_primary.dat
....................\.........\....\..........................\_primary.vhd
....................\.........\....\pixel_testbench\verilog.psm
....................\.........\....\...............\_primary.dat
....................\.........\....\...............\_primary.vhd
....................\.........\....\testbench\verilog.psm
....................\.........\....\.........\_primary.dat
....................\.........\....\.........\_primary.vhd
....................\.........\....\vga\verilog.psm
....................\.........\....\...\_primary.dat
....................\.........\....\...\_primary.vhd
....................\.........\....\_info
....................\UP_Argument_Parser.pm
....................\UP_Extras.pm
....................\UP_HDL_Parser.pm
....................\UP_HDL_Writer.pm
....................\UP_IP_Core_Generator.pl
....................\UP_PTF_Parser.pm
....................\UP_System_Info.pm
....................\testbench\work\@altera_@u@p_@v@g@a_@d@a@c
....................\.........\....\pixel_testbench
....................\.........\....\testbench
....................\.........\....\vga
....................\HAL\inc
....................\...\src
....................\testbench\work
....................\doc
....................\HAL
....................\hdl
....................\inc
....................\testbench
altera_up_avalon_vga