文件名称:HW3_P1
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Clock Controller
There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CLK”. Your design should pass a predetermined number of pulses to an output “POUT” and then stop, without producing any shortened pulses or glitches. Your circuit should have an 8 position DIP Switch for setting a number “N” and a free running clock input that has a frequency is of 2.55 Mhz . The “START” signal is an asynchronous input signal which will initiate the generator such that when the start button is pushed exactly N clock pulses would be passed to the output “POUT”. -Clock Controller
There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CLK”. Your design should pass a predetermined number of pulses to an output “POUT” and then stop, without producing any shortened pulses or glitches. Your circuit should have an 8 position DIP Switch for setting a number “N” and a free running clock input that has a frequency is of 2.55 Mhz . The “START” signal is an asynchronous input signal which will initiate the generator such that when the start button is pushed exactly N clock pulses would be passed to the output “POUT”.
There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CLK”. Your design should pass a predetermined number of pulses to an output “POUT” and then stop, without producing any shortened pulses or glitches. Your circuit should have an 8 position DIP Switch for setting a number “N” and a free running clock input that has a frequency is of 2.55 Mhz . The “START” signal is an asynchronous input signal which will initiate the generator such that when the start button is pushed exactly N clock pulses would be passed to the output “POUT”. -Clock Controller
There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CLK”. Your design should pass a predetermined number of pulses to an output “POUT” and then stop, without producing any shortened pulses or glitches. Your circuit should have an 8 position DIP Switch for setting a number “N” and a free running clock input that has a frequency is of 2.55 Mhz . The “START” signal is an asynchronous input signal which will initiate the generator such that when the start button is pushed exactly N clock pulses would be passed to the output “POUT”.
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下载文件列表
HW3_P1\_xmsgs
......\......\xst.xmsgs
......\clk_divider.vhd
......\HW3_P1.ise
......\HW3_P1.ntrc_log
......\HW3_P1.restore
......\HW3_P1_xdb
......\..........\tmp
......\..........\...\ise.lock
......\..........\...\ise
......\..........\...\...\__OBJSTORE__
......\..........\...\...\............\_ProjRepoInternal_
......\..........\...\...\............\Autonym
......\..........\...\...\............\common
......\..........\...\...\............\HierarchicalDesign
......\..........\...\...\............\..................\__stored_object_table__
......\..........\...\...\............\..................\HDProject
......\..........\...\...\............\..................\.........\HDProject
......\..........\...\...\............\..................\.........\HDProject_StrTbl
......\..........\...\...\............\PnAutoRun
......\..........\...\...\............\.........\Scripts
......\..........\...\...\............\.........\.......\RunOnce_tcl
......\..........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
......\..........\...\...\............\ProjectNavigator
......\..........\...\...\............\................\__stored_object_table__
......\..........\...\...\............\................\__stored_objects__
......\..........\...\...\............\................\__stored_objects___StrTbl
......\..........\...\...\............\................\dpm_project_main
......\..........\...\...\............\................\................\dpm_project_main
......\..........\...\...\............\................\................\dpm_project_main_StrTbl
......\..........\...\...\............\ProjectNavigatorGui
......\..........\...\...\............\...................\GuiProjectData
......\..........\...\...\............\...................\GuiProjectData_StrTbl
......\..........\...\...\............\SrcCtrl
......\..........\...\...\............\.......\SavedOptions
......\..........\...\...\............\STE
......\..........\...\...\__REGISTRY__
......\..........\...\...\............\_ProjRepoInternal_
......\..........\...\...\............\..................\regkeys
......\..........\...\...\............\Autonym
......\..........\...\...\............\.......\regkeys
......\..........\...\...\............\bitgen
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\common
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\cpldfit
......\..........\...\...\............\.......\regkeys
......\..........\...\...\............\dumpngdio
......\..........\...\...\............\.........\regkeys
......\..........\...\...\............\fuse
......\..........\...\...\............\....\regkeys
......\..........\...\...\............\HierarchicalDesign
......\..........\...\...\............\..................\HDProject
......\..........\...\...\............\..................\.........\regkeys
......\..........\...\...\............\..................\regkeys
......\..........\...\...\............\hprep6
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\idem
......\..........\...\...\............\....\regkeys
......\..........\...\...\............\map
......\..........\...\...\............\...\regkeys
......\..........\...\...\............\netgen
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\ngc2edif
......\..........\...\...\............\........\regkeys
......\..........\...\...\............\ngcbuild
......\..........\...\...\............\........\regkeys
......\..........\...\...\............\ngdbuild
......\..........\...\...\............\........\regkeys
......\..........\...\...\............\par
......\..........\...\...\............\...\regkeys
......\..........\...\...\............\ProjectNavigator
......\..........\...\...\............\................\regkeys
......\..........\...\...\............\ProjectNavigatorGui
......\..........\...\...\............\...................\regkeys
......\..........\...\...\............\ProjectSeedData
......\.....
......\......\xst.xmsgs
......\clk_divider.vhd
......\HW3_P1.ise
......\HW3_P1.ntrc_log
......\HW3_P1.restore
......\HW3_P1_xdb
......\..........\tmp
......\..........\...\ise.lock
......\..........\...\ise
......\..........\...\...\__OBJSTORE__
......\..........\...\...\............\_ProjRepoInternal_
......\..........\...\...\............\Autonym
......\..........\...\...\............\common
......\..........\...\...\............\HierarchicalDesign
......\..........\...\...\............\..................\__stored_object_table__
......\..........\...\...\............\..................\HDProject
......\..........\...\...\............\..................\.........\HDProject
......\..........\...\...\............\..................\.........\HDProject_StrTbl
......\..........\...\...\............\PnAutoRun
......\..........\...\...\............\.........\Scripts
......\..........\...\...\............\.........\.......\RunOnce_tcl
......\..........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
......\..........\...\...\............\ProjectNavigator
......\..........\...\...\............\................\__stored_object_table__
......\..........\...\...\............\................\__stored_objects__
......\..........\...\...\............\................\__stored_objects___StrTbl
......\..........\...\...\............\................\dpm_project_main
......\..........\...\...\............\................\................\dpm_project_main
......\..........\...\...\............\................\................\dpm_project_main_StrTbl
......\..........\...\...\............\ProjectNavigatorGui
......\..........\...\...\............\...................\GuiProjectData
......\..........\...\...\............\...................\GuiProjectData_StrTbl
......\..........\...\...\............\SrcCtrl
......\..........\...\...\............\.......\SavedOptions
......\..........\...\...\............\STE
......\..........\...\...\__REGISTRY__
......\..........\...\...\............\_ProjRepoInternal_
......\..........\...\...\............\..................\regkeys
......\..........\...\...\............\Autonym
......\..........\...\...\............\.......\regkeys
......\..........\...\...\............\bitgen
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\common
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\cpldfit
......\..........\...\...\............\.......\regkeys
......\..........\...\...\............\dumpngdio
......\..........\...\...\............\.........\regkeys
......\..........\...\...\............\fuse
......\..........\...\...\............\....\regkeys
......\..........\...\...\............\HierarchicalDesign
......\..........\...\...\............\..................\HDProject
......\..........\...\...\............\..................\.........\regkeys
......\..........\...\...\............\..................\regkeys
......\..........\...\...\............\hprep6
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\idem
......\..........\...\...\............\....\regkeys
......\..........\...\...\............\map
......\..........\...\...\............\...\regkeys
......\..........\...\...\............\netgen
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\ngc2edif
......\..........\...\...\............\........\regkeys
......\..........\...\...\............\ngcbuild
......\..........\...\...\............\........\regkeys
......\..........\...\...\............\ngdbuild
......\..........\...\...\............\........\regkeys
......\..........\...\...\............\par
......\..........\...\...\............\...\regkeys
......\..........\...\...\............\ProjectNavigator
......\..........\...\...\............\................\regkeys
......\..........\...\...\............\ProjectNavigatorGui
......\..........\...\...\............\...................\regkeys
......\..........\...\...\............\ProjectSeedData
......\.....