文件名称:UART

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 261kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 郭**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

用FPGA开发的串口通信的程序,代码是用verilog编写的,希望对大家有用!-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
相关搜索: uart
串口通信
uart
vhdl
code

(系统自动生成,下载前可以参看下载内容)

下载文件列表

uartverilog\db\my_uart_top.analyze_file.qmsg

...........\..\my_uart_top.asm.qmsg

...........\..\my_uart_top.asm_labs.ddb

...........\..\my_uart_top.cbx.xml

...........\..\my_uart_top.cmp.cdb

...........\..\my_uart_top.cmp.hdb

...........\..\my_uart_top.cmp.logdb

...........\..\my_uart_top.cmp.rdb

...........\..\my_uart_top.cmp.tdb

...........\..\my_uart_top.cmp0.ddb

...........\..\my_uart_top.dbp

...........\..\my_uart_top.db_info

...........\..\my_uart_top.eco.cdb

...........\..\my_uart_top.fit.qmsg

...........\..\my_uart_top.hier_info

...........\..\my_uart_top.hif

...........\..\my_uart_top.map.cdb

...........\..\my_uart_top.map.hdb

...........\..\my_uart_top.map.logdb

...........\..\my_uart_top.map.qmsg

...........\..\my_uart_top.pre_map.cdb

...........\..\my_uart_top.pre_map.hdb

...........\..\my_uart_top.psp

...........\..\my_uart_top.pss

...........\..\my_uart_top.rpp.qmsg

...........\..\my_uart_top.rtlv.hdb

...........\..\my_uart_top.rtlv_sg.cdb

...........\..\my_uart_top.rtlv_sg_swap.cdb

...........\..\my_uart_top.sgate.rvd

...........\..\my_uart_top.sgate_sm.rvd

...........\..\my_uart_top.sgdiff.cdb

...........\..\my_uart_top.sgdiff.hdb

...........\..\my_uart_top.signalprobe.cdb

...........\..\my_uart_top.sld_design_entry.sci

...........\..\my_uart_top.sld_design_entry_dsc.sci

...........\..\my_uart_top.syn_hier_info

...........\..\my_uart_top.tan.qmsg

...........\my_uart_rx.v

...........\my_uart_top.asm.rpt

...........\my_uart_top.cdf

...........\my_uart_top.done

...........\my_uart_top.dpf

...........\my_uart_top.fit.rpt

...........\my_uart_top.fit.smsg

...........\my_uart_top.fit.summary

...........\my_uart_top.flow.rpt

...........\my_uart_top.map.rpt

...........\my_uart_top.map.smsg

...........\my_uart_top.map.summary

...........\my_uart_top.pin

...........\my_uart_top.pof

...........\my_uart_top.qpf

...........\my_uart_top.qsf

...........\my_uart_top.qws

...........\my_uart_top.tan.rpt

...........\my_uart_top.tan.summary

...........\my_uart_top.v

...........\my_uart_tx.v

...........\speed_select.v

...........\db

uartverilog

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