文件名称:Project_WorkSpace

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 92kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • im***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

The code i have written is for the patent designed by Jay Hartvigsen, Tony Cheng, Eric Hoang and Buddy Broeker "JTAG/DEBUG INTERFACE".

This is meant for the purpose of interfacing the controller to debug its core,this code is working fine n very soon i shall be uploading the testbench also.


(系统自动生成,下载前可以参看下载内容)

下载文件列表

Project_WorkSpace\Boundary_Scan_Register.v

.................\Boundary_Scan_Register.v.bak

.................\debug_data.v

.................\debug_status.v

.................\demux.v

.................\insruction_registor.v

.................\JTAG.cr.mti

.................\JTAG.mpf

.................\mux.v

.................\TAP_Controller.v

.................\TAP_Controller.v.bak

.................\Top_module.v

.................\Top_module.v.bak

.................\vsim.wlf

.................\work

.................\....\@boundary_@scan_@register

.................\....\.........................\_primary.dat

.................\....\.........................\_primary.dbs

.................\....\.........................\_primary.vhd

.................\....\.........................\verilog.prw

.................\....\.........................\verilog.psm

.................\....\@instruction_@register

.................\....\......................\_primary.dat

.................\....\......................\_primary.dbs

.................\....\......................\_primary.vhd

.................\....\......................\verilog.prw

.................\....\......................\verilog.psm

.................\....\@t@a@p_@controller

.................\....\..................\_primary.dat

.................\....\..................\_primary.dbs

.................\....\..................\_primary.vhd

.................\....\..................\verilog.prw

.................\....\..................\verilog.psm

.................\....\@top_module

.................\....\...........\_primary.dat

.................\....\...........\_primary.dbs

.................\....\...........\_primary.vhd

.................\....\...........\verilog.prw

.................\....\...........\verilog.psm

.................\....\_info

.................\....\_temp

.................\....\.....\vlog5nst85

.................\....\.....\vlog6fant1

.................\....\.....\vlogb51dq5

.................\....\.....\vloge6ic16

.................\....\.....\vlogjzwcab

.................\....\.....\vlogtrr8v9

.................\....\.....\vlogv2q5y4

.................\....\.....\vlogw3gfx4

.................\....\_vmake

.................\....\debug_data

.................\....\..........\_primary.dat

.................\....\..........\_primary.dbs

.................\....\..........\_primary.vhd

.................\....\..........\verilog.prw

.................\....\..........\verilog.psm

.................\....\debug_status

.................\....\............\_primary.dat

.................\....\............\_primary.dbs

.................\....\............\_primary.vhd

.................\....\............\verilog.prw

.................\....\............\verilog.psm

.................\....\demux

.................\....\.....\_primary.dat

.................\....\.....\_primary.dbs

.................\....\.....\_primary.vhd

.................\....\.....\verilog.prw

.................\....\.....\verilog.psm

.................\....\mux

.................\....\...\_primary.dat

.................\....\...\_primary.dbs

.................\....\...\_primary.vhd

.................\....\...\verilog.prw

.................\....\...\verilog.psm

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