文件名称:clk_div16
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一个用VHDL语言编写的1/16分频器，后续还有计数器、数据选择器、七段数码显示程序等软件平台是Quartus II 7.2 ，最后通过这些小的模块可以组合起来制作出一个时钟或者其它的任意进制计数器，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -Written in VHDL language using a 1/16 divider, follow-up there is the counter, data selector, seven-segment digital display procedures, the software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner s sense of achievement and motivation in learning . All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
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下载文件列表
qq clk_div16\clk_div16.asm.rpt
............\clk_div16.bsf
............\clk_div16.done
............\clk_div16.fit.rpt
............\clk_div16.fit.smsg
............\clk_div16.fit.summary
............\clk_div16.flow.rpt
............\clk_div16.map.rpt
............\clk_div16.map.summary
............\clk_div16.pin
............\clk_div16.qpf
............\clk_div16.qsf
............\clk_div16.qws
............\clk_div16.sim.rpt
............\clk_div16.tan.rpt
............\clk_div16.tan.summary
............\clk_div16.vhd
............\clk_div16.vwf
............\db\clk_div16.asm.qmsg
............\..\clk_div16.cbx.xml
............\..\clk_div16.cmp.bpm
............\..\clk_div16.cmp.cdb
............\..\clk_div16.cmp.ecobp
............\..\clk_div16.cmp.hdb
............\..\clk_div16.cmp.logdb
............\..\clk_div16.cmp.rdb
............\..\clk_div16.cmp.tdb
............\..\clk_div16.cmp0.ddb
............\..\clk_div16.cmp_bb.cdb
............\..\clk_div16.cmp_bb.hdb
............\..\clk_div16.cmp_bb.logdb
............\..\clk_div16.cmp_bb.rcf
............\..\clk_div16.dbp
............\..\clk_div16.db_info
............\..\clk_div16.eco.cdb
............\..\clk_div16.eds_overflow
............\..\clk_div16.fit.qmsg
............\..\clk_div16.hier_info
............\..\clk_div16.hif
............\..\clk_div16.map.bpm
............\..\clk_div16.map.cdb
............\..\clk_div16.map.ecobp
............\..\clk_div16.map.hdb
............\..\clk_div16.map.logdb
............\..\clk_div16.map.qmsg
............\..\clk_div16.map_bb.cdb
............\..\clk_div16.map_bb.hdb
............\..\clk_div16.map_bb.logdb
............\..\clk_div16.pre_map.cdb
............\..\clk_div16.pre_map.hdb
............\..\clk_div16.psp
............\..\clk_div16.pss
............\..\clk_div16.rtlv.hdb
............\..\clk_div16.rtlv_sg.cdb
............\..\clk_div16.rtlv_sg_swap.cdb
............\..\clk_div16.sgdiff.cdb
............\..\clk_div16.sgdiff.hdb
............\..\clk_div16.signalprobe.cdb
............\..\clk_div16.sim.cvwf
............\..\clk_div16.sim.hdb
............\..\clk_div16.sim.qmsg
............\..\clk_div16.sim.rdb
............\..\clk_div16.sld_design_entry.sci
............\..\clk_div16.sld_design_entry_dsc.sci
............\..\clk_div16.syn_hier_info
............\..\clk_div16.tan.qmsg
............\..\clk_div16.tis_db_list.ddb
............\..\prev_cmp_clk_div16.qmsg
............\..\wed.wsf
............\db
qq clk_div16
............\clk_div16.bsf
............\clk_div16.done
............\clk_div16.fit.rpt
............\clk_div16.fit.smsg
............\clk_div16.fit.summary
............\clk_div16.flow.rpt
............\clk_div16.map.rpt
............\clk_div16.map.summary
............\clk_div16.pin
............\clk_div16.qpf
............\clk_div16.qsf
............\clk_div16.qws
............\clk_div16.sim.rpt
............\clk_div16.tan.rpt
............\clk_div16.tan.summary
............\clk_div16.vhd
............\clk_div16.vwf
............\db\clk_div16.asm.qmsg
............\..\clk_div16.cbx.xml
............\..\clk_div16.cmp.bpm
............\..\clk_div16.cmp.cdb
............\..\clk_div16.cmp.ecobp
............\..\clk_div16.cmp.hdb
............\..\clk_div16.cmp.logdb
............\..\clk_div16.cmp.rdb
............\..\clk_div16.cmp.tdb
............\..\clk_div16.cmp0.ddb
............\..\clk_div16.cmp_bb.cdb
............\..\clk_div16.cmp_bb.hdb
............\..\clk_div16.cmp_bb.logdb
............\..\clk_div16.cmp_bb.rcf
............\..\clk_div16.dbp
............\..\clk_div16.db_info
............\..\clk_div16.eco.cdb
............\..\clk_div16.eds_overflow
............\..\clk_div16.fit.qmsg
............\..\clk_div16.hier_info
............\..\clk_div16.hif
............\..\clk_div16.map.bpm
............\..\clk_div16.map.cdb
............\..\clk_div16.map.ecobp
............\..\clk_div16.map.hdb
............\..\clk_div16.map.logdb
............\..\clk_div16.map.qmsg
............\..\clk_div16.map_bb.cdb
............\..\clk_div16.map_bb.hdb
............\..\clk_div16.map_bb.logdb
............\..\clk_div16.pre_map.cdb
............\..\clk_div16.pre_map.hdb
............\..\clk_div16.psp
............\..\clk_div16.pss
............\..\clk_div16.rtlv.hdb
............\..\clk_div16.rtlv_sg.cdb
............\..\clk_div16.rtlv_sg_swap.cdb
............\..\clk_div16.sgdiff.cdb
............\..\clk_div16.sgdiff.hdb
............\..\clk_div16.signalprobe.cdb
............\..\clk_div16.sim.cvwf
............\..\clk_div16.sim.hdb
............\..\clk_div16.sim.qmsg
............\..\clk_div16.sim.rdb
............\..\clk_div16.sld_design_entry.sci
............\..\clk_div16.sld_design_entry_dsc.sci
............\..\clk_div16.syn_hier_info
............\..\clk_div16.tan.qmsg
............\..\clk_div16.tis_db_list.ddb
............\..\prev_cmp_clk_div16.qmsg
............\..\wed.wsf
............\db
qq clk_div16