文件名称:cml
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 248kb
- 下载次数：
- 0次
- 提 供 者：
- cheng******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
基于Verilog的数字基带通信系统
3. 项目描述：本系统为通信原理课程设计课题之一，用Verilog语言编写数字基带通信系统的应用程序，完成P=31的m序列的生成，并进行HDB3编码传输，在接收端进行译码接收。-Verilog-based digital baseband communication system 3. Project Descr iption: The system is one of the topics Communication Theory course design, using Verilog language digital baseband communication system applications, the completion of P = 31 m-sequence generation, and make HDB3 coded transmission, reception at the receiving end for decoding.
3. 项目描述：本系统为通信原理课程设计课题之一，用Verilog语言编写数字基带通信系统的应用程序，完成P=31的m序列的生成，并进行HDB3编码传输，在接收端进行译码接收。-Verilog-based digital baseband communication system 3. Project Descr iption: The system is one of the topics Communication Theory course design, using Verilog language digital baseband communication system applications, the completion of P = 31 m-sequence generation, and make HDB3 coded transmission, reception at the receiving end for decoding.
相关搜索： 数字基带
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下载文件列表
add_b.bsf
add_b.v
add_v.bsf
add_v.v
clock.bsf
clock.v
cml.asm.rpt
cml.bdf
cml.done
cml.fit.eqn
cml.fit.rpt
cml.fit.smsg
cml.fit.summary
cml.flow.rpt
cml.map.eqn
cml.map.rpt
cml.map.summary
cml.pin
cml.qpf
cml.qsf
cml.qws
cml.sim.rpt
cml.tan.rpt
cml.tan.summary
cml.vwf
cml_assignment_defaults.qdf
polar.bsf
polar.v
seqdet.bsf
seqdet.v
yima.bsf
yima.v
db\prev_cmp_cml.qmsg
..\cml.map.qmsg
..\cml.eco.cdb
..\cml.sld_design_entry.sci
..\cml.cbx.xml
..\cml.hif
..\cml.hier_info
..\cml.rtlv_sg_swap.cdb
..\cml.pre_map.hdb
..\cml.rtlv.hdb
..\cml.pre_map.cdb
..\cml.map.logdb
..\cml.psp
..\cml.pss
..\cml.dbp
..\cml.cmp.rdb
..\cml.sgdiff.hdb
..\cml.fit.qmsg
..\cml.cmp.logdb
..\cml.asm.qmsg
..\cml.syn_hier_info
..\cml.cmp0.ddb
..\cml.map.cdb
..\cml.sim.qmsg
..\cml.cmp.hdb
..\cml.rtlv_sg.cdb
..\cml.map.hdb
..\cml.tan.qmsg
..\cml.sim.cvwf
..\cml.sim.rdb
..\cml.sim.vwf
..\cml.sim.hdb
..\prev_cmp_cml.map.qmsg
..\prev_cmp_cml.sim.qmsg
..\cml.sgdiff.cdb
..\cml.cmp.cdb
..\cml.db_info
..\prev_cmp_cml.fit.qmsg
..\prev_cmp_cml.asm.qmsg
..\cml.cmp.tdb
..\prev_cmp_cml.tan.qmsg
..\cml.sld_design_entry_dsc.sci
..\cml.tis_db_list.ddb
..\cml.signalprobe.cdb
..\cml.eds_overflow
..\wed.wsf
db
add_b.v
add_v.bsf
add_v.v
clock.bsf
clock.v
cml.asm.rpt
cml.bdf
cml.done
cml.fit.eqn
cml.fit.rpt
cml.fit.smsg
cml.fit.summary
cml.flow.rpt
cml.map.eqn
cml.map.rpt
cml.map.summary
cml.pin
cml.qpf
cml.qsf
cml.qws
cml.sim.rpt
cml.tan.rpt
cml.tan.summary
cml.vwf
cml_assignment_defaults.qdf
polar.bsf
polar.v
seqdet.bsf
seqdet.v
yima.bsf
yima.v
db\prev_cmp_cml.qmsg
..\cml.map.qmsg
..\cml.eco.cdb
..\cml.sld_design_entry.sci
..\cml.cbx.xml
..\cml.hif
..\cml.hier_info
..\cml.rtlv_sg_swap.cdb
..\cml.pre_map.hdb
..\cml.rtlv.hdb
..\cml.pre_map.cdb
..\cml.map.logdb
..\cml.psp
..\cml.pss
..\cml.dbp
..\cml.cmp.rdb
..\cml.sgdiff.hdb
..\cml.fit.qmsg
..\cml.cmp.logdb
..\cml.asm.qmsg
..\cml.syn_hier_info
..\cml.cmp0.ddb
..\cml.map.cdb
..\cml.sim.qmsg
..\cml.cmp.hdb
..\cml.rtlv_sg.cdb
..\cml.map.hdb
..\cml.tan.qmsg
..\cml.sim.cvwf
..\cml.sim.rdb
..\cml.sim.vwf
..\cml.sim.hdb
..\prev_cmp_cml.map.qmsg
..\prev_cmp_cml.sim.qmsg
..\cml.sgdiff.cdb
..\cml.cmp.cdb
..\cml.db_info
..\prev_cmp_cml.fit.qmsg
..\prev_cmp_cml.asm.qmsg
..\cml.cmp.tdb
..\prev_cmp_cml.tan.qmsg
..\cml.sld_design_entry_dsc.sci
..\cml.tis_db_list.ddb
..\cml.signalprobe.cdb
..\cml.eds_overflow
..\wed.wsf
db