文件名称:ourdev_247126
介绍说明－－下载内容均来自于网络，请自行研究使用
his design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Running the Design-his design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Running the Design
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Running the Design-his design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Running the Design
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DE2_70_TV\AUDIO_DAC.v
.........\DE2_70_TV.pof
.........\DE2_70_TV.qpf
.........\DE2_70_TV.qsf
.........\DE2_70_TV.sof
.........\DE2_70_TV.v
.........\DIV.v
.........\I2C_AV_Config.v
.........\I2C_Controller.v
.........\ITU_656_Decoder.v
.........\Line_Buffer.v
.........\MAC_3.v
.........\PLL.v
.........\README.txt
.........\Reset_Delay.v
.........\Sdram_Control_4Port\command.v
.........\...................\control_interface.v
.........\...................\Sdram_Control_4Port.v
.........\...................\Sdram_Params.h
.........\...................\Sdram_PLL.bsf
.........\...................\Sdram_PLL.ppf
.........\...................\Sdram_PLL.v
.........\...................\Sdram_RD_FIFO.v
.........\...................\Sdram_WR_FIFO.v
.........\...................\sdr_data_path.v
.........\Sdram_Control_4Port
.........\SEG7_LUT.v
.........\SEG7_LUT_8.v
.........\TD_Detect.v
.........\TP_RAM.v
.........\VGA_Ctrl.v
.........\YCbCr2RGB.v
.........\YUV422_to_444.v
.........\db\DE2_70_TV.db_info
.........\..\DE2_70_TV.sld_design_entry.sci
.........\..\DE2_70_TV.eco.cdb
.........\db
.........\DE2_70_TV.qws
DE2_70_TV
.........\DE2_70_TV.pof
.........\DE2_70_TV.qpf
.........\DE2_70_TV.qsf
.........\DE2_70_TV.sof
.........\DE2_70_TV.v
.........\DIV.v
.........\I2C_AV_Config.v
.........\I2C_Controller.v
.........\ITU_656_Decoder.v
.........\Line_Buffer.v
.........\MAC_3.v
.........\PLL.v
.........\README.txt
.........\Reset_Delay.v
.........\Sdram_Control_4Port\command.v
.........\...................\control_interface.v
.........\...................\Sdram_Control_4Port.v
.........\...................\Sdram_Params.h
.........\...................\Sdram_PLL.bsf
.........\...................\Sdram_PLL.ppf
.........\...................\Sdram_PLL.v
.........\...................\Sdram_RD_FIFO.v
.........\...................\Sdram_WR_FIFO.v
.........\...................\sdr_data_path.v
.........\Sdram_Control_4Port
.........\SEG7_LUT.v
.........\SEG7_LUT_8.v
.........\TD_Detect.v
.........\TP_RAM.v
.........\VGA_Ctrl.v
.........\YCbCr2RGB.v
.........\YUV422_to_444.v
.........\db\DE2_70_TV.db_info
.........\..\DE2_70_TV.sld_design_entry.sci
.........\..\DE2_70_TV.eco.cdb
.........\db
.........\DE2_70_TV.qws
DE2_70_TV