文件名称:74HC194
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74ls194 基于verilog语言的实现 -Verilog language 74ls194 based on the realization of
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下载文件列表
74hc194
.......\74hc194.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\designer.log
.......\........\.....\shift4.adb
.......\........\.....\shift4.dtf
.......\........\.....\..........\verify.log
.......\........\.....\shift4.ide_des
.......\........\.....\shift4.pdb
.......\........\.....\shift4.pdb.depends
.......\........\.....\shift4.tcl
.......\........\.....\shift4_fp
.......\........\.....\.........\$$FlashPro_07294.L$$
.......\........\.....\.........\projectData
.......\........\.....\.........\...........\shift4.pdb
.......\........\.....\.........\shift4.log
.......\........\.....\.........\shift4.pro
.......\........\.....\simulation
.......\hdl
.......\...\74hc194.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\shift4
.......\..........\........\......\verilog.psm
.......\..........\........\......\_primary.dat
.......\..........\........\......\_primary.dbs
.......\..........\........\......\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\_vmake
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\testbench.v
.......\synthesis
.......\.........\.recordref
.......\.........\backup
.......\.........\......\shift4.srr
.......\.........\coreip
.......\.........\run_options.txt
.......\.........\shift4.areasrr
.......\.........\shift4.edn
.......\.........\shift4.fse
.......\.........\shift4.htm
.......\.........\shift4.map
.......\.........\shift4.pdc
.......\.........\shift4.sap
.......\.........\shift4.sdf
.......\.........\shift4.so
.......\.........\shift4.srd
.......\.........\shift4.srm
.......\.........\shift4.srr
.......\.........\shift4.srs
.......\.........\shift4.szr
.......\.........\shift4.tlg
.......\.........\shift4_sdc.sdc
.......\.........\shift4_syn.prj
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\sap.log
.......\.........\......\shift4.plg
.......\.........\......\shift4_flink.htm
.......\.........\......\shift4_srr.htm
.......\.........\......\shift4_toc.htm
.......\.........\traplog.tlg
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc194.pdf
.......\74hc194.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\designer.log
.......\........\.....\shift4.adb
.......\........\.....\shift4.dtf
.......\........\.....\..........\verify.log
.......\........\.....\shift4.ide_des
.......\........\.....\shift4.pdb
.......\........\.....\shift4.pdb.depends
.......\........\.....\shift4.tcl
.......\........\.....\shift4_fp
.......\........\.....\.........\$$FlashPro_07294.L$$
.......\........\.....\.........\projectData
.......\........\.....\.........\...........\shift4.pdb
.......\........\.....\.........\shift4.log
.......\........\.....\.........\shift4.pro
.......\........\.....\simulation
.......\hdl
.......\...\74hc194.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\shift4
.......\..........\........\......\verilog.psm
.......\..........\........\......\_primary.dat
.......\..........\........\......\_primary.dbs
.......\..........\........\......\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\_vmake
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\testbench.v
.......\synthesis
.......\.........\.recordref
.......\.........\backup
.......\.........\......\shift4.srr
.......\.........\coreip
.......\.........\run_options.txt
.......\.........\shift4.areasrr
.......\.........\shift4.edn
.......\.........\shift4.fse
.......\.........\shift4.htm
.......\.........\shift4.map
.......\.........\shift4.pdc
.......\.........\shift4.sap
.......\.........\shift4.sdf
.......\.........\shift4.so
.......\.........\shift4.srd
.......\.........\shift4.srm
.......\.........\shift4.srr
.......\.........\shift4.srs
.......\.........\shift4.szr
.......\.........\shift4.tlg
.......\.........\shift4_sdc.sdc
.......\.........\shift4_syn.prj
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\sap.log
.......\.........\......\shift4.plg
.......\.........\......\shift4_flink.htm
.......\.........\......\shift4_srr.htm
.......\.........\......\shift4_toc.htm
.......\.........\traplog.tlg
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc194.pdf