文件名称:risc32
介绍说明－－下载内容均来自于网络，请自行研究使用
VHDL设计实例与仿真中的32位risc代码，经仿真确定可以通过-VHDL design and simulation of the 32-bit risc code, as determined by simulation
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下载文件列表
risc32
......\alu.cmd_log
......\alu.lso
......\alu.ngc
......\alu.ngr
......\alu.prj
......\alu.spl
......\alu.stx
......\alu.sym
......\alu.syr
......\alu.vhd
......\automake.log
......\comparer.spl
......\comparer.sym
......\comparer.vhd
......\coregen.log
......\coregen.prj
......\cpu.cmd_log
......\cpu.lso
......\cpu.ngc
......\cpu.ngr
......\cpu.prj
......\cpu.spl
......\cpu.stx
......\cpu.sym
......\cpu.syr
......\cpu.vhd
......\cu.spl
......\cu.sym
......\cu.vhd
......\ir.spl
......\ir.sym
......\ir.vhd
......\mem.cmd_log
......\mem.lso
......\mem.prj
......\mem.spl
......\mem.sym
......\mem.syr
......\MEM.vhd
......\muxa.spl
......\muxa.sym
......\muxa.vhd
......\muxalu1.spl
......\muxalu1.sym
......\muxalu1.vhd
......\muxalu2.spl
......\muxalu2.sym
......\muxalu2.vhd
......\muxpcalu.spl
......\muxpcalu.sym
......\muxpcalu.vhd
......\muxwrd.spl
......\muxwrd.sym
......\muxwrd.vhd
......\pc.spl
......\pc.sym
......\pc.vhd
......\pcalu.spl
......\pcalu.sym
......\pcalu.vhd
......\pepExtractor.prj
......\regfile.spl
......\regfile.sym
......\regfile.vhd
......\risc32.dhp
......\risc32.npl
......\test_alu_vhd.fdo
......\test_alu_vhd.udo
......\test_alu_vhd.vhd
......\test_comp_vhd.vhd
......\test_cpu.vhd
......\test_cpu_vhd.fdo
......\test_cpu_vhd.udo
......\test_ir_vhd.vhd
......\test_ir_vhd_vhd.fdo
......\test_ir_vhd_vhd.udo
......\test_pcalu_vhd.vhd
......\tes_cpu.vhd
......\tets_regfile_vhd.vhd
......\transcript
......\t_cpu.ANT
......\t_cpu.fdo
......\t_cpu.jhd
......\t_cpu.tbw
......\t_cpu.udo
......\t_cpu.vhw
......\t_mem_vhd.vhd
......\t_mem_vhd_vhd.fdo
......\t_mem_vhd_vhd.udo
......\vsim.wlf
......\work
......\....\alu
......\....\...\behavioral.dat
......\....\...\behavioral.psm
......\....\...\_primary.dat
......\....\comparer
......\....\........\behavioral.dat
......\....\........\behavioral.psm
......\....\........\_primary.dat
......\alu.cmd_log
......\alu.lso
......\alu.ngc
......\alu.ngr
......\alu.prj
......\alu.spl
......\alu.stx
......\alu.sym
......\alu.syr
......\alu.vhd
......\automake.log
......\comparer.spl
......\comparer.sym
......\comparer.vhd
......\coregen.log
......\coregen.prj
......\cpu.cmd_log
......\cpu.lso
......\cpu.ngc
......\cpu.ngr
......\cpu.prj
......\cpu.spl
......\cpu.stx
......\cpu.sym
......\cpu.syr
......\cpu.vhd
......\cu.spl
......\cu.sym
......\cu.vhd
......\ir.spl
......\ir.sym
......\ir.vhd
......\mem.cmd_log
......\mem.lso
......\mem.prj
......\mem.spl
......\mem.sym
......\mem.syr
......\MEM.vhd
......\muxa.spl
......\muxa.sym
......\muxa.vhd
......\muxalu1.spl
......\muxalu1.sym
......\muxalu1.vhd
......\muxalu2.spl
......\muxalu2.sym
......\muxalu2.vhd
......\muxpcalu.spl
......\muxpcalu.sym
......\muxpcalu.vhd
......\muxwrd.spl
......\muxwrd.sym
......\muxwrd.vhd
......\pc.spl
......\pc.sym
......\pc.vhd
......\pcalu.spl
......\pcalu.sym
......\pcalu.vhd
......\pepExtractor.prj
......\regfile.spl
......\regfile.sym
......\regfile.vhd
......\risc32.dhp
......\risc32.npl
......\test_alu_vhd.fdo
......\test_alu_vhd.udo
......\test_alu_vhd.vhd
......\test_comp_vhd.vhd
......\test_cpu.vhd
......\test_cpu_vhd.fdo
......\test_cpu_vhd.udo
......\test_ir_vhd.vhd
......\test_ir_vhd_vhd.fdo
......\test_ir_vhd_vhd.udo
......\test_pcalu_vhd.vhd
......\tes_cpu.vhd
......\tets_regfile_vhd.vhd
......\transcript
......\t_cpu.ANT
......\t_cpu.fdo
......\t_cpu.jhd
......\t_cpu.tbw
......\t_cpu.udo
......\t_cpu.vhw
......\t_mem_vhd.vhd
......\t_mem_vhd_vhd.fdo
......\t_mem_vhd_vhd.udo
......\vsim.wlf
......\work
......\....\alu
......\....\...\behavioral.dat
......\....\...\behavioral.psm
......\....\...\_primary.dat
......\....\comparer
......\....\........\behavioral.dat
......\....\........\behavioral.psm
......\....\........\_primary.dat