文件名称:bitadder
介绍说明－－下载内容均来自于网络，请自行研究使用
一位全加器，VERILOG实现，包括测试文件，测试可用，欢迎下载，共同学习-A full adder, VERILOG implementation, including test papers, test available, please download, a common study
(系统自动生成,下载前可以参看下载内容)
下载文件列表
bitadder
........\Adder1Bit.v
........\Adder3Bit.v
........\test.vec
........\testbench.v
........\Adder1Bit.v
........\Adder3Bit.v
........\test.vec
........\testbench.v