文件名称:pinlvji

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 10.34mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 袁**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

用4位十进制计数器对用户输入时钟信号进行计数,计数间隔为1秒钟。计数满1秒钟后将计数值(即频率值)所存到4位寄存器中显示,并将计数器清0,在进行下一次计数。

频率计由三种模块组成:testctl为控制模块,由1Hz其准产生rst_cnt,load,cnt_en信号;cnt10为带清0及计数允许的十进制计数器;reg4b为四位寄存器。

-With four decimal counter input clock signal to the user to count, count one second interval. 1 seconds after the full count of values (that is, the frequency value) stored in the register to display 4, and Counter-ching 0, the time of the next count.

Frequency of three modules: testctl for the control module, the alignment of 1Hz generated by rst_cnt, load, cnt_en signal cnt10 with clearance for the count 0 and the decimal counter permit reg4b register for the four.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

lianxi5

.......\bj

.......\..\alt_max2.vo

.......\..\frequen_cout.acf

.......\..\frequen_cout.edf

.......\..\frequen_cout.fit

.......\..\frequen_cout.hex

.......\..\frequen_cout.hif

.......\..\frequen_cout.mmf

.......\..\frequen_cout.ndb

.......\..\frequen_cout.pin

.......\..\frequen_cout.pof

.......\..\frequen_cout.rpt

.......\..\frequen_cout.snf

.......\..\frequen_cout.sof

.......\..\frequen_cout.tcl

.......\..\frequen_cout.ttf

.......\..\frequen_cout.vo

.......\..\frequen_cout.xdb

.......\..\leospec.his

.......\hfz

.......\...\123.cr.mti

.......\...\123.mpf

.......\...\alt_max2.vo

.......\...\frequen_cout.vo

.......\...\frequen_top.v

.......\...\transcript

.......\...\vsim.wlf

.......\...\work

.......\...\....\@a@n@d1

.......\...\....\.......\verilog.asm

.......\...\....\.......\_primary.dat

.......\...\....\.......\_primary.vhd

.......\...\....\@a@n@d10

.......\...\....\........\verilog.asm

.......\...\....\........\_primary.dat

.......\...\....\........\_primary.vhd

.......\...\....\@a@n@d11

.......\...\....\........\verilog.asm

.......\...\....\........\_primary.dat

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.......\...\....\@a@n@d12

.......\...\....\........\verilog.asm

.......\...\....\........\_primary.dat

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.......\...\....\@a@n@d13

.......\...\....\........\verilog.asm

.......\...\....\........\_primary.dat

.......\...\....\........\_primary.vhd

.......\...\....\@a@n@d14

.......\...\....\........\verilog.asm

.......\...\....\........\_primary.dat

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.......\...\....\@a@n@d15

.......\...\....\........\verilog.asm

.......\...\....\........\_primary.dat

.......\...\....\........\_primary.vhd

.......\...\....\@a@n@d16

.......\...\....\........\verilog.asm

.......\...\....\........\_primary.dat

.......\...\....\........\_primary.vhd

.......\...\....\@a@n@d2

.......\...\....\.......\verilog.asm

.......\...\....\.......\_primary.dat

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.......\...\....\@a@n@d3

.......\...\....\.......\verilog.asm

.......\...\....\.......\_primary.dat

.......\...\....\.......\_primary.vhd

.......\...\....\@a@n@d4

.......\...\....\.......\verilog.asm

.......\...\....\.......\_primary.dat

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.......\...\....\@a@n@d5

.......\...\....\.......\verilog.asm

.......\...\....\.......\_primary.dat

.......\...\....\.......\_primary.vhd

.......\...\....\@a@n@d6

.......\...\....\.......\verilog.asm

.......\...\....\.......\_primary.dat

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.......\...\....\@a@n@d7

.......\...\....\.......\verilog.asm

.......\...\....\.......\_primary.dat

.......\...\....\.......\_primary.vhd

.......\...\....\@a@n@d8

.......\...\....\.......\verilog.asm

.......\...\....\.......\_primary.dat

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.......\...\....\@a@n@d9

.......\...\....\.......\verilog.asm

.......\...\....\.......\_primary.dat

.......\...\....\.......\_primary.vhd

.......\...\....\@c@l@k@l@o@c@k

.......\...\....\..............\verilog.asm

.......\...\....\..............\_primary.dat

.......\...\....\..............\_primary.vhd

.......\...\....\@d@e@l@a@y

.......\...\....\..........\verilog.asm

.......\...\....\..........\_primary.dat

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