文件名称:CAN_IP
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这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
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CAN
...\bench
...\.....\verilog
...\.....\.......\can_testbench.v
...\.....\.......\can_testbench_defines.v
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\timescale.v
...\rtl
...\...\verilog
...\...\.......\can_acf.v
...\...\.......\can_bsp.v
...\...\.......\can_btl.v
...\...\.......\can_crc.v
...\...\.......\can_defines.v
...\...\.......\can_fifo.v
...\...\.......\can_ibo.v
...\...\.......\can_register.v
...\...\.......\can_registers.v
...\...\.......\can_register_asyn.v
...\...\.......\can_register_asyn_syn.v
...\...\.......\can_register_syn.v
...\...\.......\can_top.v
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\README.txt
...\bench
...\.....\verilog
...\.....\.......\can_testbench.v
...\.....\.......\can_testbench_defines.v
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\timescale.v
...\rtl
...\...\verilog
...\...\.......\can_acf.v
...\...\.......\can_bsp.v
...\...\.......\can_btl.v
...\...\.......\can_crc.v
...\...\.......\can_defines.v
...\...\.......\can_fifo.v
...\...\.......\can_ibo.v
...\...\.......\can_register.v
...\...\.......\can_registers.v
...\...\.......\can_register_asyn.v
...\...\.......\can_register_asyn_syn.v
...\...\.......\can_register_syn.v
...\...\.......\can_top.v
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\README.txt