文件名称:EP1C6Q240-8REG_WR
介绍说明－－下载内容均来自于网络，请自行研究使用
altera公司的FPGA的一些开发用的VHDL的源代码用于学习-altera INC. develop fpga vhdl source for study and research
(系统自动生成,下载前可以参看下载内容)
下载文件列表
reg_wr
......\74138_0.vhd
......\a.v
......\a.vhd
......\aa.v
......\bt.bsf
......\bt.cmp
......\bt.vhd
......\cmp_state.ini
......\db
......\..\test.asm.qmsg
......\..\test.cbx.xml
......\..\test.cmp.cdb
......\..\test.cmp.hdb
......\..\test.cmp.qrpt
......\..\test.cmp.rdb
......\..\test.cmp.tdb
......\..\test.cmp0.ddb
......\..\test.dbp
......\..\test.db_info
......\..\test.eco.cdb
......\..\test.eds_overflow
......\..\test.fit.qmsg
......\..\test.hier_info
......\..\test.hif
......\..\test.map.cdb
......\..\test.map.hdb
......\..\test.map.qmsg
......\..\test.pre_map.cdb
......\..\test.pre_map.hdb
......\..\test.psp
......\..\test.rtlv.hdb
......\..\test.rtlv_sg.cdb
......\..\test.rtlv_sg_swap.cdb
......\..\test.sgdiff.cdb
......\..\test.sgdiff.hdb
......\..\test.signalprobe.cdb
......\..\test.sim.hdb
......\..\test.sim.qmsg
......\..\test.sim.qrpt
......\..\test.sim.rdb
......\..\test.sim.vwf
......\..\test.sld_design_entry.sci
......\..\test.sld_design_entry_dsc.sci
......\..\test.smp_dump.txt
......\..\test.syn_hier_info
......\..\test.tan.qmsg
......\..\test_cmp.qrpt
......\..\test_sim.qrpt
......\..\wed.zsf
......\ff.bsf
......\ff.cmp
......\ff.vhd
......\ff_waveforms.html
......\int.bsf
......\int.vhd
......\int.vhd.bak
......\interrupt.bsf
......\interrupt.vhd
......\pllll.bsf
......\pllll.cmp
......\pllll.ppf
......\pllll.vhd
......\pllll_waveforms.html
......\read.bsf
......\read.vhd
......\Rint.bsf
......\Rint.vhd
......\sim.cfg
......\test.asm.rpt
......\test.bdf
......\test.cdf
......\test.done
......\test.dpf
......\test.fit.eqn
......\test.fit.rpt
......\test.fit.smsg
......\test.fit.summary
......\test.fld
......\test.flow.rpt
......\test.map.eqn
......\test.map.rpt
......\test.map.summary
......\test.pin
......\test.pof
......\test.qpf
......\test.qsf
......\test.qsf.bak
......\test.qws
......\test.sim.rpt
......\test.sof
......\test.tan.rpt
......\test.tan.summary
......\test.tcl
......\test.vhd
......\test.vwf
......\test_assignment_defaults.qdf
......\tTRI.bsf
......\74138_0.vhd
......\a.v
......\a.vhd
......\aa.v
......\bt.bsf
......\bt.cmp
......\bt.vhd
......\cmp_state.ini
......\db
......\..\test.asm.qmsg
......\..\test.cbx.xml
......\..\test.cmp.cdb
......\..\test.cmp.hdb
......\..\test.cmp.qrpt
......\..\test.cmp.rdb
......\..\test.cmp.tdb
......\..\test.cmp0.ddb
......\..\test.dbp
......\..\test.db_info
......\..\test.eco.cdb
......\..\test.eds_overflow
......\..\test.fit.qmsg
......\..\test.hier_info
......\..\test.hif
......\..\test.map.cdb
......\..\test.map.hdb
......\..\test.map.qmsg
......\..\test.pre_map.cdb
......\..\test.pre_map.hdb
......\..\test.psp
......\..\test.rtlv.hdb
......\..\test.rtlv_sg.cdb
......\..\test.rtlv_sg_swap.cdb
......\..\test.sgdiff.cdb
......\..\test.sgdiff.hdb
......\..\test.signalprobe.cdb
......\..\test.sim.hdb
......\..\test.sim.qmsg
......\..\test.sim.qrpt
......\..\test.sim.rdb
......\..\test.sim.vwf
......\..\test.sld_design_entry.sci
......\..\test.sld_design_entry_dsc.sci
......\..\test.smp_dump.txt
......\..\test.syn_hier_info
......\..\test.tan.qmsg
......\..\test_cmp.qrpt
......\..\test_sim.qrpt
......\..\wed.zsf
......\ff.bsf
......\ff.cmp
......\ff.vhd
......\ff_waveforms.html
......\int.bsf
......\int.vhd
......\int.vhd.bak
......\interrupt.bsf
......\interrupt.vhd
......\pllll.bsf
......\pllll.cmp
......\pllll.ppf
......\pllll.vhd
......\pllll_waveforms.html
......\read.bsf
......\read.vhd
......\Rint.bsf
......\Rint.vhd
......\sim.cfg
......\test.asm.rpt
......\test.bdf
......\test.cdf
......\test.done
......\test.dpf
......\test.fit.eqn
......\test.fit.rpt
......\test.fit.smsg
......\test.fit.summary
......\test.fld
......\test.flow.rpt
......\test.map.eqn
......\test.map.rpt
......\test.map.summary
......\test.pin
......\test.pof
......\test.qpf
......\test.qsf
......\test.qsf.bak
......\test.qws
......\test.sim.rpt
......\test.sof
......\test.tan.rpt
......\test.tan.summary
......\test.tcl
......\test.vhd
......\test.vwf
......\test_assignment_defaults.qdf
......\tTRI.bsf