文件名称:can
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基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
(系统自动生成,下载前可以参看下载内容)
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can
...\bench
...\.....\CVS
...\.....\...\Entries
...\.....\...\Repository
...\.....\...\Root
...\.....\...\Template
...\.....\verilog
...\.....\.......\can_testbench.v
...\.....\.......\can_testbench_defines.v
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\...\Template
...\.....\.......\timescale.v
...\can_testbench.v
...\can_testbench_defines.v
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\...\Template
...\doc
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\...\Template
...\...\src
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\...\Template
...\rtl
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\...\Template
...\...\verilog
...\...\.......\can_acf.v
...\...\.......\can_bsp.v
...\...\.......\can_btl.v
...\...\.......\can_crc.v
...\...\.......\can_defines.v
...\...\.......\can_fifo.v
...\...\.......\can_ibo.v
...\...\.......\can_register.v
...\...\.......\can_registers.v
...\...\.......\can_register_asyn.v
...\...\.......\can_register_asyn_syn.v
...\...\.......\can_register_syn.v
...\...\.......\can_top.v
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\...\Template
...\...\.......\README.txt
...\sim
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\...\Template
...\...\rtl_sim
...\...\.......\bin
...\...\.......\...\cds.lib
...\...\.......\...\CVS
...\...\.......\...\...\Entries
...\...\.......\...\...\Repository
...\...\.......\...\...\Root
...\...\.......\...\...\Template
...\...\.......\...\hdl.var
...\...\.......\...\INCA_libs
...\...\.......\...\.........\CVS
...\...\.......\...\.........\...\Entries
...\...\.......\...\.........\...\Repository
...\...\.......\...\.........\...\Root
...\...\.......\...\.........\...\Template
...\...\.......\...\.........\worklib
...\...\.......\...\.........\.......\CVS
...\...\.......\...\.........\.......\...\Entries
...\...\.......\...\.........\.......\...\Repository
...\...\.......\...\.........\.......\...\Root
...\...\.......\...\.........\.......\...\Template
...\...\.......\...\.........\.......\dir_keeper
...\...\.......\...\memory_file_list
...\...\.......\...\rtl_file_list
...\...\.......\...\sim_file_list
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\...\Template
...\...\.......\log
...\...\.......\...\CVS
...\...\.......\...\...\Entries
...\bench
...\.....\CVS
...\.....\...\Entries
...\.....\...\Repository
...\.....\...\Root
...\.....\...\Template
...\.....\verilog
...\.....\.......\can_testbench.v
...\.....\.......\can_testbench_defines.v
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\...\Template
...\.....\.......\timescale.v
...\can_testbench.v
...\can_testbench_defines.v
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\...\Template
...\doc
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\...\Template
...\...\src
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\...\Template
...\rtl
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\...\Template
...\...\verilog
...\...\.......\can_acf.v
...\...\.......\can_bsp.v
...\...\.......\can_btl.v
...\...\.......\can_crc.v
...\...\.......\can_defines.v
...\...\.......\can_fifo.v
...\...\.......\can_ibo.v
...\...\.......\can_register.v
...\...\.......\can_registers.v
...\...\.......\can_register_asyn.v
...\...\.......\can_register_asyn_syn.v
...\...\.......\can_register_syn.v
...\...\.......\can_top.v
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\...\Template
...\...\.......\README.txt
...\sim
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\...\Template
...\...\rtl_sim
...\...\.......\bin
...\...\.......\...\cds.lib
...\...\.......\...\CVS
...\...\.......\...\...\Entries
...\...\.......\...\...\Repository
...\...\.......\...\...\Root
...\...\.......\...\...\Template
...\...\.......\...\hdl.var
...\...\.......\...\INCA_libs
...\...\.......\...\.........\CVS
...\...\.......\...\.........\...\Entries
...\...\.......\...\.........\...\Repository
...\...\.......\...\.........\...\Root
...\...\.......\...\.........\...\Template
...\...\.......\...\.........\worklib
...\...\.......\...\.........\.......\CVS
...\...\.......\...\.........\.......\...\Entries
...\...\.......\...\.........\.......\...\Repository
...\...\.......\...\.........\.......\...\Root
...\...\.......\...\.........\.......\...\Template
...\...\.......\...\.........\.......\dir_keeper
...\...\.......\...\memory_file_list
...\...\.......\...\rtl_file_list
...\...\.......\...\sim_file_list
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\...\Template
...\...\.......\log
...\...\.......\...\CVS
...\...\.......\...\...\Entries