文件名称:Static_PLL
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静态pll实验程序，在actel的fusion系列FPGA中综合通过-Pll static experimental procedures, the fusion line in the Actel FPGA integrated through
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下载文件列表
Static_PLL
..........\component
..........\constraint
..........\coreconsole
..........\designer
..........\........\impl1
..........\........\.....\designer.log
..........\........\.....\PLL_0P75M.ide_des
..........\........\.....\PLL_top.adb
..........\........\.....\PLL_top.dtf
..........\........\.....\...........\verify.log
..........\........\.....\PLL_top.ide_des
..........\........\.....\PLL_top.pdb
..........\........\.....\PLL_top.pdb.depends
..........\........\.....\PLL_top.tcl
..........\........\.....\simulation
..........\hdl
..........\...\88.v
..........\...\ctrl_PLL.v
..........\...\PLL_top.v
..........\phy_synthesis
..........\simulation
..........\..........\modelsim.ini
..........\..........\modelsim.ini.sav
..........\smartgen
..........\........\PLL_0P75M
..........\........\.........\PLL_0P75M.cxf
..........\........\.........\PLL_0P75M.gen
..........\........\.........\PLL_0P75M.log
..........\........\.........\PLL_0P75M.v
..........\........\PLL_0P75M_work.ixf
..........\........\smartgen.aws
..........\Static_PLL.prj
..........\stimulus
..........\synthesis
..........\.........\.recordref
..........\.........\backup
..........\.........\......\PLL_top.srr
..........\.........\coreip
..........\.........\PLL_top.areasrr
..........\.........\PLL_top.edn
..........\.........\PLL_top.map
..........\.........\PLL_top.pdc
..........\.........\PLL_top.sdf
..........\.........\PLL_top.so
..........\.........\PLL_top.srd
..........\.........\PLL_top.srm
..........\.........\PLL_top.srr
..........\.........\PLL_top.srs
..........\.........\PLL_top.szr
..........\.........\PLL_top.tlg
..........\.........\PLL_top_sdc.sdc
..........\.........\PLL_top_syn.prj
..........\.........\run_options.txt
..........\.........\stdout.log
..........\.........\syntmp
..........\.........\......\PLL_top.plg
..........\.........\traplog.tlg
..........\viewdraw
..........\........\sch
..........\........\sym
..........\........\vf
..........\........\..\project.lst
..........\........\viewdraw.ini
..........\........\wir
..........\component
..........\constraint
..........\coreconsole
..........\designer
..........\........\impl1
..........\........\.....\designer.log
..........\........\.....\PLL_0P75M.ide_des
..........\........\.....\PLL_top.adb
..........\........\.....\PLL_top.dtf
..........\........\.....\...........\verify.log
..........\........\.....\PLL_top.ide_des
..........\........\.....\PLL_top.pdb
..........\........\.....\PLL_top.pdb.depends
..........\........\.....\PLL_top.tcl
..........\........\.....\simulation
..........\hdl
..........\...\88.v
..........\...\ctrl_PLL.v
..........\...\PLL_top.v
..........\phy_synthesis
..........\simulation
..........\..........\modelsim.ini
..........\..........\modelsim.ini.sav
..........\smartgen
..........\........\PLL_0P75M
..........\........\.........\PLL_0P75M.cxf
..........\........\.........\PLL_0P75M.gen
..........\........\.........\PLL_0P75M.log
..........\........\.........\PLL_0P75M.v
..........\........\PLL_0P75M_work.ixf
..........\........\smartgen.aws
..........\Static_PLL.prj
..........\stimulus
..........\synthesis
..........\.........\.recordref
..........\.........\backup
..........\.........\......\PLL_top.srr
..........\.........\coreip
..........\.........\PLL_top.areasrr
..........\.........\PLL_top.edn
..........\.........\PLL_top.map
..........\.........\PLL_top.pdc
..........\.........\PLL_top.sdf
..........\.........\PLL_top.so
..........\.........\PLL_top.srd
..........\.........\PLL_top.srm
..........\.........\PLL_top.srr
..........\.........\PLL_top.srs
..........\.........\PLL_top.szr
..........\.........\PLL_top.tlg
..........\.........\PLL_top_sdc.sdc
..........\.........\PLL_top_syn.prj
..........\.........\run_options.txt
..........\.........\stdout.log
..........\.........\syntmp
..........\.........\......\PLL_top.plg
..........\.........\traplog.tlg
..........\viewdraw
..........\........\sch
..........\........\sym
..........\........\vf
..........\........\..\project.lst
..........\........\viewdraw.ini
..........\........\wir