文件名称:Examples
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几个简单的verilog代码，推荐用modelsim工具学习-A few simple Verilog code, recommended by ModelSim tools to learn
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下载文件列表
Examples
........\abc_100.v
........\analog.spj
........\analog.v
........\code_coverage.spj
........\code_coverage.v
........\code_coverage2.spj
........\design.lib
........\design.sdf
........\design.sym
........\design.v
........\design1
........\design2
........\faulttst.v
........\fltsim.spj
........\gate.spj
........\rtl.sym
........\rtl_.spj
........\rtl_err.spj
........\stimulus.v
........\stimulus.v1
........\testbench.v
........\testbench2.v
........\vend.gv
........\vend.v
........\venderr.v
........\vending.fsm
........\vending.spj
........\vending.sym
........\vending.v
........\vending_testbench.v
........\vendtest.v
........\abc_100.v
........\analog.spj
........\analog.v
........\code_coverage.spj
........\code_coverage.v
........\code_coverage2.spj
........\design.lib
........\design.sdf
........\design.sym
........\design.v
........\design1
........\design2
........\faulttst.v
........\fltsim.spj
........\gate.spj
........\rtl.sym
........\rtl_.spj
........\rtl_err.spj
........\stimulus.v
........\stimulus.v1
........\testbench.v
........\testbench2.v
........\vend.gv
........\vend.v
........\venderr.v
........\vending.fsm
........\vending.spj
........\vending.sym
........\vending.v
........\vending_testbench.v
........\vendtest.v