文件名称:VHDL
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采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下：
1.系统主时钟为100 MHz。
2.数据为16位-数据线上连续2次00FF后数据传输开始。
3.系统内部总线宽度为8位。
4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。
5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。
6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束，可以重新设定SEL的值选择下一个通道。模块数据线为8位，显示器件为4个8段LED。
7.数据采集模式如下：单通道采集（由SEL信号选择通道），多通道顺次采集（当前通道采满后转入下一通道），多通道并行采集（每通道依次采集一个数据）。模式由控制信号MODE选择，采集数据的总个数由NUM_COLLECT给出。
8.数据采集过程中不能读取，数据读取过程中不能采集-err
1.系统主时钟为100 MHz。
2.数据为16位-数据线上连续2次00FF后数据传输开始。
3.系统内部总线宽度为8位。
4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。
5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。
6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束，可以重新设定SEL的值选择下一个通道。模块数据线为8位，显示器件为4个8段LED。
7.数据采集模式如下：单通道采集（由SEL信号选择通道），多通道顺次采集（当前通道采满后转入下一通道），多通道并行采集（每通道依次采集一个数据）。模式由控制信号MODE选择，采集数据的总个数由NUM_COLLECT给出。
8.数据采集过程中不能读取，数据读取过程中不能采集-err
相关搜索： VHDL
VHDL-FPGA-Verilog
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数据
采集
fpga
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模块
vhdl
数据采集
VHDL-FPGA-Verilog
VHDL-FPGA-Verilog
采集
VHDL-FPGA-Verilog
vhdl
数据
采集
fpga
vhdl
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rar
模块
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数据采集
VHDL-FPGA-Verilog
VHDL-FPGA-Verilog
采集
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下载文件列表
期末报告
........\4通道的数据采集控制模块.doc
........\DAQ_pengfu
........\..........\.untf
........\..........\automake.log
........\..........\clk_div_10.bld
........\..........\clk_div_10.cmd_log
........\..........\clk_div_10.isim_stx_prj
........\..........\clk_div_10.isim_stx_sim
........\..........\clk_div_10.lso
........\..........\clk_div_10.ngc
........\..........\clk_div_10.ngd
........\..........\clk_div_10.ngr
........\..........\clk_div_10.prj
........\..........\clk_div_10.spl
........\..........\clk_div_10.stx
........\..........\clk_div_10.sym
........\..........\clk_div_10.syr
........\..........\clk_div_10.vhd
........\..........\clk_div_10_stx.prj
........\..........\clk_div_10_summary.html
........\..........\cnt1_0.cmd_log
........\..........\cnt1_0.lso
........\..........\cnt1_0.ngc
........\..........\cnt1_0.ngr
........\..........\cnt1_0.prj
........\..........\cnt1_0.spl
........\..........\cnt1_0.stx
........\..........\cnt1_0.sym
........\..........\cnt1_0.syr
........\..........\cnt1_0.vhd
........\..........\cnt1_0_summary.html
........\..........\DAQ_pengfu.dhp
........\..........\DAQ_pengfu.ise
........\..........\DAQ_pengfu.ise_ISE_Backup
........\..........\DAQ_pengfu.sch
........\..........\DAQ_pengfu._u_
........\..........\DAQ_Sch.cmd_log
........\..........\DAQ_Sch.sch
........\..........\DAQ_Sch.schbak
........\..........\DAQ_Sch.schcmd
........\..........\DAQ_Sch.schlog
........\..........\DAQ_Sch.sym
........\..........\DAQ_Sch.vhf
........\..........\DAQ_Sch._u_
........\..........\eight_0.sch
........\..........\eight_0S.cmd_log
........\..........\eight_0S.lso
........\..........\eight_0S.ngc
........\..........\eight_0S.ngr
........\..........\eight_0S.prj
........\..........\eight_0S.sch
........\..........\eight_0S.schbak
........\..........\eight_0S.schcmd
........\..........\eight_0S.schlog
........\..........\eight_0S.stx
........\..........\eight_0S.sym
........\..........\eight_0S.symbak
........\..........\eight_0S.symcmd
........\..........\eight_0S.symlog
........\..........\eight_0S.syr
........\..........\eight_0S.vhf
........\..........\eight_0S._u_
........\..........\eight_0S_summary.html
........\..........\eight_8S.sch
........\..........\eigth_0.sch
........\..........\eitht_1S.cmd_log
........\..........\eitht_1S.lso
........\..........\eitht_1S.ngc
........\..........\eitht_1S.ngr
........\..........\eitht_1S.prj
........\..........\eitht_1S.sch
........\..........\eitht_1S.schbak
........\..........\eitht_1S.schcmd
........\..........\eitht_1S.stx
........\..........\eitht_1S.sym
........\..........\eitht_1S.symbak
........\..........\eitht_1S.symcmd
........\..........\eitht_1S.symlog
........\..........\eitht_1S.syr
........\..........\eitht_1S.vhf
........\..........\eitht_1S._u_
........\..........\eitht_1S_summary.html
........\..........\eitht_1s_vhdl.prj
........\..........\fourth_1.cmd_log
........\..........\fourth_1.lso
........\..........\fourth_1.ngc
........\..........\fourth_1.ngr
........\..........\fourth_1.prj
........\..........\fourth_1.spl
........\..........\fourth_1.stx
........\..........\fourth_1.sym
........\..........\fourth_1.syr
........\..........\FOURTH_1.vhd
........\..........\fourth_1_summary.html
........\..........\fourth_1_vhdl.prj
........\..........\four_0.ant
........\..........\four_0.cmd_log
........\..........\FOUR_0.DIA
........\..........\four_0.isim_stx_prj
........\4通道的数据采集控制模块.doc
........\DAQ_pengfu
........\..........\.untf
........\..........\automake.log
........\..........\clk_div_10.bld
........\..........\clk_div_10.cmd_log
........\..........\clk_div_10.isim_stx_prj
........\..........\clk_div_10.isim_stx_sim
........\..........\clk_div_10.lso
........\..........\clk_div_10.ngc
........\..........\clk_div_10.ngd
........\..........\clk_div_10.ngr
........\..........\clk_div_10.prj
........\..........\clk_div_10.spl
........\..........\clk_div_10.stx
........\..........\clk_div_10.sym
........\..........\clk_div_10.syr
........\..........\clk_div_10.vhd
........\..........\clk_div_10_stx.prj
........\..........\clk_div_10_summary.html
........\..........\cnt1_0.cmd_log
........\..........\cnt1_0.lso
........\..........\cnt1_0.ngc
........\..........\cnt1_0.ngr
........\..........\cnt1_0.prj
........\..........\cnt1_0.spl
........\..........\cnt1_0.stx
........\..........\cnt1_0.sym
........\..........\cnt1_0.syr
........\..........\cnt1_0.vhd
........\..........\cnt1_0_summary.html
........\..........\DAQ_pengfu.dhp
........\..........\DAQ_pengfu.ise
........\..........\DAQ_pengfu.ise_ISE_Backup
........\..........\DAQ_pengfu.sch
........\..........\DAQ_pengfu._u_
........\..........\DAQ_Sch.cmd_log
........\..........\DAQ_Sch.sch
........\..........\DAQ_Sch.schbak
........\..........\DAQ_Sch.schcmd
........\..........\DAQ_Sch.schlog
........\..........\DAQ_Sch.sym
........\..........\DAQ_Sch.vhf
........\..........\DAQ_Sch._u_
........\..........\eight_0.sch
........\..........\eight_0S.cmd_log
........\..........\eight_0S.lso
........\..........\eight_0S.ngc
........\..........\eight_0S.ngr
........\..........\eight_0S.prj
........\..........\eight_0S.sch
........\..........\eight_0S.schbak
........\..........\eight_0S.schcmd
........\..........\eight_0S.schlog
........\..........\eight_0S.stx
........\..........\eight_0S.sym
........\..........\eight_0S.symbak
........\..........\eight_0S.symcmd
........\..........\eight_0S.symlog
........\..........\eight_0S.syr
........\..........\eight_0S.vhf
........\..........\eight_0S._u_
........\..........\eight_0S_summary.html
........\..........\eight_8S.sch
........\..........\eigth_0.sch
........\..........\eitht_1S.cmd_log
........\..........\eitht_1S.lso
........\..........\eitht_1S.ngc
........\..........\eitht_1S.ngr
........\..........\eitht_1S.prj
........\..........\eitht_1S.sch
........\..........\eitht_1S.schbak
........\..........\eitht_1S.schcmd
........\..........\eitht_1S.stx
........\..........\eitht_1S.sym
........\..........\eitht_1S.symbak
........\..........\eitht_1S.symcmd
........\..........\eitht_1S.symlog
........\..........\eitht_1S.syr
........\..........\eitht_1S.vhf
........\..........\eitht_1S._u_
........\..........\eitht_1S_summary.html
........\..........\eitht_1s_vhdl.prj
........\..........\fourth_1.cmd_log
........\..........\fourth_1.lso
........\..........\fourth_1.ngc
........\..........\fourth_1.ngr
........\..........\fourth_1.prj
........\..........\fourth_1.spl
........\..........\fourth_1.stx
........\..........\fourth_1.sym
........\..........\fourth_1.syr
........\..........\FOURTH_1.vhd
........\..........\fourth_1_summary.html
........\..........\fourth_1_vhdl.prj
........\..........\four_0.ant
........\..........\four_0.cmd_log
........\..........\FOUR_0.DIA
........\..........\four_0.isim_stx_prj