altera_maxII_PCI_Verilog

........................\cmp_state.ini

........................\core

........................\....\t32.bsf

........................\....\t32.cmp

........................\....\t32.html

........................\....\t32.inc

........................\....\t32.v

........................\....\t32.vo

........................\....\t32_bb.v

........................\....\t32_inst.v

........................\db

........................\..\top_pci32.cmp.rdb

........................\..\top_pci32.db_info

........................\..\top_pci32.eco.cdb

........................\..\top_pci32.hif

........................\..\top_pci32.map.hdb

........................\..\top_pci32.map.qmsg

........................\..\top_pci32.sld_design_entry.sci

........................\..\top_pci32.sld_design_entry_dsc.sci

........................\local

........................\.....\lcd_cntrl.v

........................\.....\mem_cntrl.v

........................\.....\perip.v

........................\.....\temp_cntrl.v

........................\.....\top_local.v

........................\readme.txt

........................\top_pci32.flow.rpt

........................\top_pci32.map.rpt

........................\top_pci32.map.summary

........................\top_pci32.qpf

........................\top_pci32.qsf

........................\top_pci32.qws

........................\top_pci32.v