文件名称:vga_timing_gen
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog文件 实现VGA时序驱动，产生vsync和hsync信号。附有自检测程序。-Verilog file to achieve VGA timing-driven, resulting in VSYNC and HSYNC signals. With self-testing procedures.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
tb_video_timing_gen.v
test_chk_dist.v
test_chk_if_val_occ_insim.v
test_chk_pls_wd.v
video_timing_gen.v
test_chk_dist.v
test_chk_if_val_occ_insim.v
test_chk_pls_wd.v
video_timing_gen.v