文件名称:disanci
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5位的操作数X和Y输入后暂存在寄存器A和B中，两位的操作控制码control暂存在寄存器C中，按照control码的不同，分布实现下列操作：
00控制X+Y
01控制X-Y
10控制X and Y
11控制 X xor Y
运算结果暂存在寄存器D中，然后输出。
-5 of the operand X and Y after the temporary importation of A and B in the register, the two operational control code register C in temporary control, in accordance with the control code is different from the distribution of the realization of the following steps: 00 control X+ Y01 control of X- Y10 control X and Y11 control X xor Y computing the results of temporary storage in the register D, and then output.
00控制X+Y
01控制X-Y
10控制X and Y
11控制 X xor Y
运算结果暂存在寄存器D中，然后输出。
-5 of the operand X and Y after the temporary importation of A and B in the register, the two operational control code register C in temporary control, in accordance with the control code is different from the distribution of the realization of the following steps: 00 control X+ Y01 control of X- Y10 control X and Y11 control X xor Y computing the results of temporary storage in the register D, and then output.
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disanci
.......\asd.ant
.......\asd.tbw
.......\asd.vhw
.......\asd.xwv
.......\asd.xwv_bak
.......\asd_bencher.prj
.......\automake.log
.......\disanci.dhp
.......\disanci.ise
.......\disanci.ise_ISE_Backup
.......\isim
.......\....\temp
.......\....\....\hdllib.ref
.......\....\....\hdpdeps.ref
.......\....\....\sub00
.......\....\....\.....\vhpl00.vho
.......\....\....\.....\vhpl01.vho
.......\....\work
.......\....\....\hdllib.ref
.......\....\....\hdpdeps.ref
.......\....\....\logic
.......\....\....\.....\behavioral.h
.......\....\....\.....\entity.cpp
.......\....\....\.....\entity.h
.......\....\....\.....\mingw
.......\....\....\.....\.....\behavioral.obj
.......\....\....\qwe
.......\....\....\...\entity.cpp
.......\....\....\...\entity.h
.......\....\....\...\mingw
.......\....\....\...\.....\testbench_arch.obj
.......\....\....\...\testbench_arch.h
.......\....\....\...\xsimtestbench_arch.cpp
.......\....\....\sub00
.......\....\....\.....\vhpl00.vho
.......\....\....\.....\vhpl01.vho
.......\....\....\.....\vhpl02.vho
.......\....\....\.....\vhpl03.vho
.......\....\....\.....\vhpl04.vho
.......\....\....\.....\vhpl05.vho
.......\....\....\wave
.......\....\....\....\entity.cpp
.......\....\....\....\entity.h
.......\....\....\....\mingw
.......\....\....\....\testbench_arch.h
.......\isim.cmd
.......\isim.hdlsourcefiles
.......\isim.tmp_save
.......\.............\_1
.......\isimwavedata.xwv
.......\logic.cmd_log
.......\logic.isim_stx_prj
.......\logic.isim_stx_sim
.......\logic.lso
.......\logic.ngr
.......\logic.prj
.......\logic.spl
.......\logic.stx
.......\logic.sym
.......\logic.syr
.......\logic.vhd
.......\logic_ise6_bak.zip
.......\logic_stx.prj
.......\logic_summary.html
.......\pepExtractor.prj
.......\prjname.lso
.......\qwe.ant
.......\qwe.isim_beh_exe
.......\qwe.isim_beh_log
.......\qwe.isim_beh_prj
.......\qwe.jhd
.......\qwe.tbw
.......\qwe.vhw
.......\qwe.xwv
.......\qwe.xwv_bak
.......\qwe_beh.prj
.......\qwe_bencher.prj
.......\qwe_isim_beh.exe
.......\transcript
.......\WAVE.ant
.......\WAVE.isim_beh_prj
.......\WAVE.tbw
.......\WAVE.vhw
.......\WAVE.xwv
.......\WAVE.xwv_bak
.......\WAVE_beh.prj
.......\WAVE_bencher.prj
.......\xilinxsim.ini
.......\xst
.......\...\dump.xst
.......\...\........\logic.prj
.......\...\........\.........\ngx
.......\...\........\.........\...\notopt
.......\...\........\.........\...\opt
.......\...\work
.......\...\....\hdllib.ref
.......\...\....\hdpdeps.ref
.......\...\....\sub00
.......\...\....\.....\vhpl00.vho
.......\asd.ant
.......\asd.tbw
.......\asd.vhw
.......\asd.xwv
.......\asd.xwv_bak
.......\asd_bencher.prj
.......\automake.log
.......\disanci.dhp
.......\disanci.ise
.......\disanci.ise_ISE_Backup
.......\isim
.......\....\temp
.......\....\....\hdllib.ref
.......\....\....\hdpdeps.ref
.......\....\....\sub00
.......\....\....\.....\vhpl00.vho
.......\....\....\.....\vhpl01.vho
.......\....\work
.......\....\....\hdllib.ref
.......\....\....\hdpdeps.ref
.......\....\....\logic
.......\....\....\.....\behavioral.h
.......\....\....\.....\entity.cpp
.......\....\....\.....\entity.h
.......\....\....\.....\mingw
.......\....\....\.....\.....\behavioral.obj
.......\....\....\qwe
.......\....\....\...\entity.cpp
.......\....\....\...\entity.h
.......\....\....\...\mingw
.......\....\....\...\.....\testbench_arch.obj
.......\....\....\...\testbench_arch.h
.......\....\....\...\xsimtestbench_arch.cpp
.......\....\....\sub00
.......\....\....\.....\vhpl00.vho
.......\....\....\.....\vhpl01.vho
.......\....\....\.....\vhpl02.vho
.......\....\....\.....\vhpl03.vho
.......\....\....\.....\vhpl04.vho
.......\....\....\.....\vhpl05.vho
.......\....\....\wave
.......\....\....\....\entity.cpp
.......\....\....\....\entity.h
.......\....\....\....\mingw
.......\....\....\....\testbench_arch.h
.......\isim.cmd
.......\isim.hdlsourcefiles
.......\isim.tmp_save
.......\.............\_1
.......\isimwavedata.xwv
.......\logic.cmd_log
.......\logic.isim_stx_prj
.......\logic.isim_stx_sim
.......\logic.lso
.......\logic.ngr
.......\logic.prj
.......\logic.spl
.......\logic.stx
.......\logic.sym
.......\logic.syr
.......\logic.vhd
.......\logic_ise6_bak.zip
.......\logic_stx.prj
.......\logic_summary.html
.......\pepExtractor.prj
.......\prjname.lso
.......\qwe.ant
.......\qwe.isim_beh_exe
.......\qwe.isim_beh_log
.......\qwe.isim_beh_prj
.......\qwe.jhd
.......\qwe.tbw
.......\qwe.vhw
.......\qwe.xwv
.......\qwe.xwv_bak
.......\qwe_beh.prj
.......\qwe_bencher.prj
.......\qwe_isim_beh.exe
.......\transcript
.......\WAVE.ant
.......\WAVE.isim_beh_prj
.......\WAVE.tbw
.......\WAVE.vhw
.......\WAVE.xwv
.......\WAVE.xwv_bak
.......\WAVE_beh.prj
.......\WAVE_bencher.prj
.......\xilinxsim.ini
.......\xst
.......\...\dump.xst
.......\...\........\logic.prj
.......\...\........\.........\ngx
.......\...\........\.........\...\notopt
.......\...\........\.........\...\opt
.......\...\work
.......\...\....\hdllib.ref
.......\...\....\hdpdeps.ref
.......\...\....\sub00
.......\...\....\.....\vhpl00.vho