文件名称:2DPSK
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用vhdl语言实现2DPSK数字传输-VHDL language used to achieve digital transmission 2DPSK
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下载文件列表
谭述润04005026杨俊义04005336朱星星04005203
..........................................\数字调制解调器.doc
..........................................\程序
..........................................\....\设计
..........................................\....\....\Creativity
..........................................\....\....\..........\channel_choice.v
..........................................\....\....\..........\clk_div.v
..........................................\....\....\..........\demodulate.v
..........................................\....\....\..........\diff_code.v
..........................................\....\....\..........\diff_code.v.bak
..........................................\....\....\..........\dig_display.v
..........................................\....\....\..........\dig_filter.v
..........................................\....\....\..........\DPSK.v
..........................................\....\....\..........\DPSK_shell.v
..........................................\....\....\..........\DPSK_shell.v.bak
..........................................\....\....\..........\generate_dm.v
..........................................\....\....\..........\generate_dm.vwf
..........................................\....\....\..........\get_edge.v
..........................................\....\....\..........\instantiation_1to4.v
..........................................\....\....\..........\key_buffer.v
..........................................\....\....\..........\lcd.vhd
..........................................\....\....\..........\lcd.vhd.bak
..........................................\....\....\..........\lcdcont.vhd
..........................................\....\....\..........\lcdcont.vhd.bak
..........................................\....\....\..........\LCM.v
..........................................\....\....\..........\LCM_pre.v
..........................................\....\....\..........\LCM_pre.v.bak
..........................................\....\....\..........\modulate.v
..........................................\....\....\..........\my_dff.v
..........................................\....\....\..........\my_shift_reg.v
..........................................\....\....\..........\my_syn_counter.v
..........................................\....\....\..........\my_trigger.v
..........................................\....\....\..........\pass_buffer.v
..........................................\....\....\..........\pass_buffer_8bit.v
..........................................\....\....\..........\phase_counter.v
..........................................\....\....\..........\phase_counter.v.bak
..........................................\....\....\..........\phase_table.v
..........................................\....\....\..........\shift_detect.v
..........................................\....\....\..........\synchronize.v
..........................................\....\....\Document
..........................................\....\....\........\CPLD板端口设计.doc
..........................................\....\....\........\CPLD母版与模拟电路子板的连接协议.doc
..........................................\....\....\........\DPSK数字端集成调试.doc
..........................................\....\....\........\DPSK调制解调器设计.doc
..........................................\....\....\........\DPSK调制解调器设计文档.doc
..........................................\....\....\DPSK
..........................................\....\....\....\Chain1.cdf
..........................................\....\....\....\Chain_DPSK.cdf
..........................................\....\....\....\channel_choice.vwf
..........................................\....\....\....\clk_div.sim.vwf
..........................................\....\....\....\clk_div.vwf
..........................................\....\....\....\cmp_state.ini
..........................................\....\....\....\db
..........................................\....\....\....\..\.cbx.xml
..........................................\....\....\....\..\ad
..........................................\数字调制解调器.doc
..........................................\程序
..........................................\....\设计
..........................................\....\....\Creativity
..........................................\....\....\..........\channel_choice.v
..........................................\....\....\..........\clk_div.v
..........................................\....\....\..........\demodulate.v
..........................................\....\....\..........\diff_code.v
..........................................\....\....\..........\diff_code.v.bak
..........................................\....\....\..........\dig_display.v
..........................................\....\....\..........\dig_filter.v
..........................................\....\....\..........\DPSK.v
..........................................\....\....\..........\DPSK_shell.v
..........................................\....\....\..........\DPSK_shell.v.bak
..........................................\....\....\..........\generate_dm.v
..........................................\....\....\..........\generate_dm.vwf
..........................................\....\....\..........\get_edge.v
..........................................\....\....\..........\instantiation_1to4.v
..........................................\....\....\..........\key_buffer.v
..........................................\....\....\..........\lcd.vhd
..........................................\....\....\..........\lcd.vhd.bak
..........................................\....\....\..........\lcdcont.vhd
..........................................\....\....\..........\lcdcont.vhd.bak
..........................................\....\....\..........\LCM.v
..........................................\....\....\..........\LCM_pre.v
..........................................\....\....\..........\LCM_pre.v.bak
..........................................\....\....\..........\modulate.v
..........................................\....\....\..........\my_dff.v
..........................................\....\....\..........\my_shift_reg.v
..........................................\....\....\..........\my_syn_counter.v
..........................................\....\....\..........\my_trigger.v
..........................................\....\....\..........\pass_buffer.v
..........................................\....\....\..........\pass_buffer_8bit.v
..........................................\....\....\..........\phase_counter.v
..........................................\....\....\..........\phase_counter.v.bak
..........................................\....\....\..........\phase_table.v
..........................................\....\....\..........\shift_detect.v
..........................................\....\....\..........\synchronize.v
..........................................\....\....\Document
..........................................\....\....\........\CPLD板端口设计.doc
..........................................\....\....\........\CPLD母版与模拟电路子板的连接协议.doc
..........................................\....\....\........\DPSK数字端集成调试.doc
..........................................\....\....\........\DPSK调制解调器设计.doc
..........................................\....\....\........\DPSK调制解调器设计文档.doc
..........................................\....\....\DPSK
..........................................\....\....\....\Chain1.cdf
..........................................\....\....\....\Chain_DPSK.cdf
..........................................\....\....\....\channel_choice.vwf
..........................................\....\....\....\clk_div.sim.vwf
..........................................\....\....\....\clk_div.vwf
..........................................\....\....\....\cmp_state.ini
..........................................\....\....\....\db
..........................................\....\....\....\..\.cbx.xml
..........................................\....\....\....\..\ad