1.利用FLEX10KE系列（EPM10K100EQC240-1X）的CLOCKBOOST

（symbol:CLKLOCK）,设计一个2倍频器，再将该倍频器2分频后输出。

对其进行时序仿真。



2.设计一个数据宽度8bit，深度是16的

同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。

要求FIFO的读写时钟频率为20MHz，

将1－16连续写入FIFO，写满后再将其读出来（读空为止）。

仿真上述逻辑的时序，将仿真波形打印出来（与第1题放在同一个PROJECT中）。



3.设计一个数据宽度8bit，深度是16的异步FIFO（读写时钟不相同），

当读写时钟的频率分别为wrclk＝40MHz、rdclk＝20MHz时，仿真其逻辑波形。

-1. FLEX10KE series using (EPM10K100EQC240-1X) of CLOCKBOOST (symbol: CLKLOCK), the design of a 2 frequency multiplier, and then the multiplier 2 hours after the output frequency. Its timing simulation. 2. The design of a data width of 8bit, depth of 16 synchronous FIFO (read and write with the same clock), with EMPTY, FULL output signs. FIFO read and write requests of the clock frequency of 20MHz, the 1-16 consecutive write FIFO, written after the read (read until empty). Simulation of the above-mentioned logical timing, simulation waveforms will print out (with the No. 1 title on the same PROJECT in). 3. To design a data width of 8bit, the depth is 16 asynchronous FIFO (read and write clock is not the same), when read and write clock frequencies were wrclk = 40MHz, rdclk = 20MHz, the simulation waveform of its logic.