文件名称:vga
- 所属分类：
- 编程文档
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 102kb
- 下载次数：
- 0次
- 提 供 者：
- cheng*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
VGA驱动及显示程序，用Verilog编写代码实现VGA的驱动和显示，并且提供了测试程序Testbench通过测试能得到正确的时序波形。-the source code for driving VGA and displaying the images,the testbench was offered.
相关搜索： vga
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下载文件列表
vga
...\automake.log
...\coregen.log
...\coregen.prj
...\generic_dpram.v
...\generic_spram.v
...\prjname.lso
...\sync_check.v
...\tests.v
...\test_bench_top.v
...\timescale.v
...\vga.dhp
...\vga.npl
...\vga_clkgen.v
...\vga_colproc.v
...\vga_csm_pb.v
...\vga_curproc.v
...\vga_cur_cregs.v
...\vga_defines.v
...\vga_enh_top.cmd_log
...\vga_enh_top.lso
...\vga_enh_top.prj
...\vga_enh_top.stx
...\vga_enh_top.syr
...\vga_enh_top.v
...\vga_enh_top_vhdl.prj
...\vga_fifo.v
...\vga_fifo_dc.v
...\vga_pgen.v
...\vga_tgen.v
...\vga_vtim.v
...\vga_wb_master.v
...\vga_wb_slave.v
...\wb_b3_check.v
...\wb_mast_model.v
...\wb_model_defines.v
...\wb_slv_model.v
...\xst
...\...\work
...\...\....\hdllib.ref
...\...\....\vlg04
...\...\....\.....\vga_wb_slave.bin
...\...\....\vlg05
...\...\....\.....\vga_wb_master.bin
...\...\....\vlg07
...\...\....\.....\vga_fifo_dc.bin
...\...\....\.....\vga_pgen.bin
...\...\....\vlg34
...\...\....\.....\generic_dpram.bin
...\...\....\vlg4D
...\...\....\.....\vga_csm_pb.bin
...\...\....\.....\vga_vtim.bin
...\...\....\vlg53
...\...\....\.....\generic_spram.bin
...\...\....\vlg59
...\...\....\.....\vga_clkgen.bin
...\...\....\vlg5D
...\...\....\.....\vga_fifo.bin
...\...\....\vlg5F
...\...\....\.....\vga_colproc.bin
...\...\....\vlg6A
...\...\....\.....\vga_enh_top.bin
...\...\....\vlg7B
...\...\....\.....\vga_tgen.bin
...\__projnav
...\.........\coregen.rsp
...\.........\runXst_tcl.rsp
...\.........\vga.gfl
...\.........\vga_enh_top.xst
...\.........\vga_flowplus.gfl
...\.........\xst_sprjTOstx_tcl.rsp
...\__projnav.log
...\automake.log
...\coregen.log
...\coregen.prj
...\generic_dpram.v
...\generic_spram.v
...\prjname.lso
...\sync_check.v
...\tests.v
...\test_bench_top.v
...\timescale.v
...\vga.dhp
...\vga.npl
...\vga_clkgen.v
...\vga_colproc.v
...\vga_csm_pb.v
...\vga_curproc.v
...\vga_cur_cregs.v
...\vga_defines.v
...\vga_enh_top.cmd_log
...\vga_enh_top.lso
...\vga_enh_top.prj
...\vga_enh_top.stx
...\vga_enh_top.syr
...\vga_enh_top.v
...\vga_enh_top_vhdl.prj
...\vga_fifo.v
...\vga_fifo_dc.v
...\vga_pgen.v
...\vga_tgen.v
...\vga_vtim.v
...\vga_wb_master.v
...\vga_wb_slave.v
...\wb_b3_check.v
...\wb_mast_model.v
...\wb_model_defines.v
...\wb_slv_model.v
...\xst
...\...\work
...\...\....\hdllib.ref
...\...\....\vlg04
...\...\....\.....\vga_wb_slave.bin
...\...\....\vlg05
...\...\....\.....\vga_wb_master.bin
...\...\....\vlg07
...\...\....\.....\vga_fifo_dc.bin
...\...\....\.....\vga_pgen.bin
...\...\....\vlg34
...\...\....\.....\generic_dpram.bin
...\...\....\vlg4D
...\...\....\.....\vga_csm_pb.bin
...\...\....\.....\vga_vtim.bin
...\...\....\vlg53
...\...\....\.....\generic_spram.bin
...\...\....\vlg59
...\...\....\.....\vga_clkgen.bin
...\...\....\vlg5D
...\...\....\.....\vga_fifo.bin
...\...\....\vlg5F
...\...\....\.....\vga_colproc.bin
...\...\....\vlg6A
...\...\....\.....\vga_enh_top.bin
...\...\....\vlg7B
...\...\....\.....\vga_tgen.bin
...\__projnav
...\.........\coregen.rsp
...\.........\runXst_tcl.rsp
...\.........\vga.gfl
...\.........\vga_enh_top.xst
...\.........\vga_flowplus.gfl
...\.........\xst_sprjTOstx_tcl.rsp
...\__projnav.log