三路智力竞赛抢答器，利用VHDL设计抢答器的各个模块，并使用EDA 工具对各模块进行仿真验证。智力竞赛抢答器的设计分为四个模块：鉴别锁存模块；答题计时模块；抢答计分模块以及扫描显示模块。把各个模块整合后，通过电路的输入输出对应关系连接起来。设计成一个有如下功能的抢答器：

（1）具有第一抢答信号的鉴别锁存功能。在主持人发出抢答指令后，若有参赛者按抢答器按钮，则该组指示灯亮，数码管显示出抢答者的组别。同时电路处于自锁状态，使其他组的抢答器按钮不起作用。

（2）具有计分功能。在初始状态时，主持人可以设置答题时间的初始值。在主持人对抢答组别进行确认，并给出倒计时计数开始信号以后，抢答者开始回答问题。此时，数码管从初始值开始计时，计至0时停止计数。

（3）具有计分功能。在初始状态时，主持人可以给每组设置初始分值。由主持人打分，答对一次加1分阶段。

（4）扫描显示功能。在初始状态时，各组计分给出一个固定的值并将它扫描显示在数码管上，当计分或者要显示的数据发生变化时，再次扫描并显示出来。

-Answer quiz three-way, and the use of VHDL design of each module s Answer, and the use of EDA tools for simulation of the module. Answer quiz design is divided into four modules: the differential latch module　answer time module　Answer scoring module and scanning module. The integration of each module through the input and output circuits connect the corresponding relations. Designed as a function of the Answer the following devices:

(1) Answer with the first differential signal latch function. Answer sent in the host command, if the participants by the Answer button, the group of bright lights, digital display of the group Answer. At the same time, the state of the circuit in a self-locking, so that other groups do not work the Answer button.

(2) scoring function. In the initial state, the host can set the initial value of Examination Time. Answer the host of the group to confirm and count the beginning of the countdown signals are given, the Answer to answer questions from the b