文件名称:ECP_LabVIEW_7.1_Starting_Point
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- [LabVIEW]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1.8mb
- 下载次数：
- 0次
- 提 供 者：
- ri***
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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下载文件列表
ECP_205_Torsional_Plant-Example
...............................\ECP 205 1DOF Phase Lead.vi
...............................\FPGA Personality
...............................\................\ECP Timed (FPGA) sync 205.vi
...............................\................\ECP205.lep
...............................\................\loop time check (u32) & overload.vi
...............................\Sub VI's
...............................\........\Bode Data.vi
...............................\........\Create Time.vi
...............................\........\Data Management.vi
...............................\........\ECP-205-FPGA-HW-Ref.ctl
...............................\........\FPGA In 205.vi
...............................\........\FPGA IO 205.vi
...............................\........\Frequency Response.vi
...............................\........\Plot Properties.vi
...............................\........\Repeat Signal.vi
...............................\........\State Feedback Compensator.vi
...............................\........\State Machine 205.vi
...............................\........\State Machine 210.vi
...............................\........\State Machine.vi
...............................\........\Swing-Up.vi
...............................\........\Test Signals.vi
...............................\........\Time Response.vi
ECP_210_Rectilinear_Plant-Example
.................................\ECP 210 1DOF PID.vi
.................................\FPGA Personality
.................................\................\ECP Timed (FPGA) sync 210.vi
.................................\................\ECP210.lep
.................................\................\loop time check (u32) & overload.vi
.................................\Sub VI's
.................................\........\Bode Data.vi
.................................\........\Create Time.vi
.................................\........\Data Management.vi
.................................\........\ECP-210-FPGA-HW-Ref.ctl
.................................\........\FPGA In 210.vi
.................................\........\FPGA IO 210.vi
.................................\........\Frequency Response.vi
.................................\........\Plot Properties.vi
.................................\........\Repeat Signal.vi
.................................\........\State Feedback Compensator.vi
.................................\........\State Machine 210.vi
.................................\........\State Machine.vi
.................................\........\Swing-Up.vi
.................................\........\Test Signals.vi
.................................\........\Time Response.vi
...............................\ECP 205 1DOF Phase Lead.vi
...............................\FPGA Personality
...............................\................\ECP Timed (FPGA) sync 205.vi
...............................\................\ECP205.lep
...............................\................\loop time check (u32) & overload.vi
...............................\Sub VI's
...............................\........\Bode Data.vi
...............................\........\Create Time.vi
...............................\........\Data Management.vi
...............................\........\ECP-205-FPGA-HW-Ref.ctl
...............................\........\FPGA In 205.vi
...............................\........\FPGA IO 205.vi
...............................\........\Frequency Response.vi
...............................\........\Plot Properties.vi
...............................\........\Repeat Signal.vi
...............................\........\State Feedback Compensator.vi
...............................\........\State Machine 205.vi
...............................\........\State Machine 210.vi
...............................\........\State Machine.vi
...............................\........\Swing-Up.vi
...............................\........\Test Signals.vi
...............................\........\Time Response.vi
ECP_210_Rectilinear_Plant-Example
.................................\ECP 210 1DOF PID.vi
.................................\FPGA Personality
.................................\................\ECP Timed (FPGA) sync 210.vi
.................................\................\ECP210.lep
.................................\................\loop time check (u32) & overload.vi
.................................\Sub VI's
.................................\........\Bode Data.vi
.................................\........\Create Time.vi
.................................\........\Data Management.vi
.................................\........\ECP-210-FPGA-HW-Ref.ctl
.................................\........\FPGA In 210.vi
.................................\........\FPGA IO 210.vi
.................................\........\Frequency Response.vi
.................................\........\Plot Properties.vi
.................................\........\Repeat Signal.vi
.................................\........\State Feedback Compensator.vi
.................................\........\State Machine 210.vi
.................................\........\State Machine.vi
.................................\........\Swing-Up.vi
.................................\........\Test Signals.vi
.................................\........\Time Response.vi