完整的CPLD/FPGA设计流程包括：• 设计定义与输入；• 功能仿真；• 逻辑综合与优化；• 综合后仿真；• 实现（适配）；• 布线后仿真（时序仿真）；• 下载调试-Integrity of the CPLD/FPGA design flow, including: •　the design of the definition of the input　•　functional simulation　•　logic synthesis and optimization　•　After comprehensive simulation　•　the realization of (adapter)　•　After wiring simulation (timing simulation)　•　Download debugging