文件名称:bijiaoqi
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pci 32位的core的实现源代码，我晕阿，实在是不好怎么说阿-pci 32-bit core of the realization of the source code, I fainted Ah, how to say it is not Arab. . . .
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ss
..\data_hex4x4.txt
..\lev.v
..\max.v
..\rom_wave_out.v
..\top.cr.mti
..\top.mpf
..\top.v
..\top_tb.v
..\vsim.wlf
..\work
..\....\lev
..\....\...\verilog.asm
..\....\...\_primary.dat
..\....\...\_primary.vhd
..\....\max
..\....\...\verilog.asm
..\....\...\_primary.dat
..\....\...\_primary.vhd
..\....\rom_wave_out
..\....\............\verilog.asm
..\....\............\_primary.dat
..\....\............\_primary.vhd
..\....\top
..\....\...\verilog.asm
..\....\...\_primary.dat
..\....\...\_primary.vhd
..\....\top_tb
..\....\......\verilog.asm
..\....\......\_primary.dat
..\....\......\_primary.vhd
..\....\_info
..\data_hex4x4.txt
..\lev.v
..\max.v
..\rom_wave_out.v
..\top.cr.mti
..\top.mpf
..\top.v
..\top_tb.v
..\vsim.wlf
..\work
..\....\lev
..\....\...\verilog.asm
..\....\...\_primary.dat
..\....\...\_primary.vhd
..\....\max
..\....\...\verilog.asm
..\....\...\_primary.dat
..\....\...\_primary.vhd
..\....\rom_wave_out
..\....\............\verilog.asm
..\....\............\_primary.dat
..\....\............\_primary.vhd
..\....\top
..\....\...\verilog.asm
..\....\...\_primary.dat
..\....\...\_primary.vhd
..\....\top_tb
..\....\......\verilog.asm
..\....\......\_primary.dat
..\....\......\_primary.vhd
..\....\_info