在用VHDL语言描述一个计数器时，如果使用了程序包ieee.std_logic_unsigned，则在描述计数器时就可以使用其中的函数“+”（递增计数）和“-”（递减计数）。假定设计对象是增1计数器并且计数器被说明为向量，则当所有位均为‘1’时，计数器的下一状态将自动变成‘0’。举例来说，假定计数器的值到达“111”是将停止，则在增1之前必须测试计数器的值。

如果计数器被说明为整数类型，则必须有上限值测试。否则，在计数顺值等于7，并且要执行增1操作时，模拟器将指出此时有错误发生

-VHDL language used to describe a counter, if used the package ieee.std_logic_unsigned, counters in the descr iption of which can be used when the function "+"　(count increments) and "-"　(decrease count). By the assumption that the design is a counter and that counter was for the vector, then when all the spaces are' 1 ' , the counter will automatically become the next state' 0' . For example, assume that the value of counter to " 111"　is to stop, then prior to the test by a counter value. If the counter has been that an integer type, there must be limits on testing. Otherwise, the count value of 7-shun, and to be implemented by 1 operation, at this time simulator will be pointed out that an error occurred