文件名称:counter16

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 83kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • PUDN*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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一个verilog源代码,作用是计数器的建模。-A verilog source code, the role of the counter model.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

counter16

.........\ISE

.........\...\counter16_top.v

.........\...\...............\.untf

.........\...\...............\automake.log

.........\...\...............\bitgen.ut

.........\...\...............\counter16.v

.........\...\...............\counter16_top.bgn

.........\...\...............\counter16_top.bit

.........\...\...............\counter16_top.bld

.........\...\...............\counter16_top.cmd_log

.........\...\...............\counter16_top.dhp

.........\...\...............\counter16_top.drc

.........\...\...............\counter16_top.lfp

.........\...\...............\counter16_top.lso

.........\...\...............\counter16_top.mrp

.........\...\...............\counter16_top.nc1

.........\...\...............\counter16_top.ncd

.........\...\...............\counter16_top.ngc

.........\...\...............\counter16_top.ngd

.........\...\...............\counter16_top.ngm

.........\...\...............\counter16_top.ngr

.........\...\...............\counter16_top.npl

.........\...\...............\counter16_top.pad

.........\...\...............\counter16_top.pad_txt

.........\...\...............\counter16_top.par

.........\...\...............\counter16_top.pcf

.........\...\...............\counter16_top.placed_ncd_tracker

.........\...\...............\counter16_top.prj

.........\...\...............\counter16_top.routed_ncd_tracker

.........\...\...............\counter16_top.stx

.........\...\...............\counter16_top.syr

.........\...\...............\counter16_top.twr

.........\...\...............\counter16_top.twx

.........\...\...............\counter16_top.ucf

.........\...\...............\counter16_top.ucf.untf

.........\...\...............\counter16_top.ut

.........\...\...............\counter16_top.v

.........\...\...............\counter16_top.xpi

.........\...\...............\counter16_top_map.ncd

.........\...\...............\counter16_top_map.ngm

.........\...\...............\counter16_top_pad.csv

.........\...\...............\counter16_top_pad.txt

.........\...\...............\counter16_top_vhdl.prj

.........\...\...............\xst

.........\...\...............\...\work

.........\...\...............\...\....\hdllib.ref

.........\...\...............\...\....\vlg3B

.........\...\...............\...\....\.....\counter16.bin

.........\...\...............\...\....\vlg5D

.........\...\...............\...\....\.....\counter16_top.bin

.........\...\...............\_ngo

.........\...\...............\....\netlist.lst

.........\...\...............\__projnav

.........\...\...............\.........\bitgen.rsp

.........\...\...............\.........\counter16_top.gfl

.........\...\...............\.........\counter16_top.xst

.........\...\...............\.........\counter16_top_flowplus.gfl

.........\...\...............\.........\counter16_top_ncdTOut_tcl.rsp

.........\...\...............\.........\ednTOngd_tcl.rsp

.........\...\...............\.........\map.log

.........\...\...............\.........\nc1TOncd_tcl.rsp

.........\...\...............\.........\par.log

.........\...\...............\.........\parentAssignPackagePinsApp_tcl.rsp

.........\...\...............\.........\posttrc.log

.........\...\...............\.........\runXst_tcl.rsp

.........\...\...............\__projnav.log

.........\modelsim

.........\........\counter16.cr.mti

.........\........\counter16.mpf

.........\........\vsim.wlf

.........\........\work

.........\........\....\counter16

.........\........\....\.........\verilog.asm

.........\........\....\.........\_primary.dat

.........\........\....\.........\_primary.vhd

.........\........\....\tb_counter16

.........\........\....\............\verilog.asm

.........\........\....\............\_primary.dat

.........\........\....\............\_primary.vhd

.........\........\....\_info

.........\rtl

.........\...\counter16.v

.........\...\counter16_top.v

.........\...\tb_counter16.v

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