文件名称:hssdrc_latest.tar
介绍说明－－下载内容均来自于网络，请自行研究使用
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
(系统自动生成,下载前可以参看下载内容)
下载文件列表
hssdrc_latest.tar